RM41L232 datasheet(79/108 Pages) TI1

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RM41L232

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SPNS240A – OCTOBER 2014 – REVISED JUNE 2015

Table 7-8. Dynamic Characteristics for the N2HET Input Capture Functionality

PARAMETER

MIN(1) (2)

MAX(1) (2)

UNIT

Input signal period, PCNT or WCAP for rising edge

(hr)(lr) tc(VCLK2) + 2

225(hr)(lr)tc(VCLK2) - 2

to rising edge

Input signal period, PCNT or WCAP for falling edge

(hr) (lr) tc(VCLK2) + 2

225 (hr)(lr) tc(VCLK2) - 2

to falling edge

Input signal high phase, PCNT or WCAP for rising

2(hr) tc(VCLK2) + 2

225 (hr)(lr) tc(VCLK2) - 2

edge to falling edge

Input signal low phase, PCNT or WCAP for falling

2(hr) tc(VCLK2) + 2

225 (hr)(lr) tc(VCLK2) - 2

edge to rising edge

(1)

hr = High-resolution prescaler, configured using the HRPFC field of the Prescale Factor Register (HETPFR).

(2)

lr = Loop-resolution prescaler, configured using the LFPRC field of the Prescale Factor Register (HETPFR).

7.4.4

N2HET Checking

7.4.4.1

Output Monitoring using Dual Clock Comparator (DCC)

N2HET[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure

the frequency of the pulse-width modulated (PWM) signal on N2HET[31].

N2HET[31] can be configured to be an internal-only channel. That is, the connection to the DCC module is

made directly from the output of the N2HET module (from the input of the output buffer).

For more information on DCC, see Section 6.6.3.

7.4.5

Disabling N2HET Outputs

Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET

module provides this capability through the "Pin Disable" input signal. This signal, when driven low,

causes the N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated.

For more details on the "N2HET Pin Disable" feature, see the device-specific Technical Reference Manual

listed in Section 8.2.1.

GIOA[5] and EQEPERR are connected to the "Pin Disable" input for N2HET. In the case of GIOA[5]

connection, this connection is made from the output of the input buffer. In the case of EQEPERR, the

EQEPERR output signal is asserted in the event of a phase error. This signal is inverted and double-

synchronized to VCLK2 for input into the N2HET PIN_nDISABLE port.

The PIN_nDISABLE port input source is selectable between the GIOA[5] and EQEPERR sources. This is

achieved through the PINMMR9[1:0] bits.

Peripheral Information and Electrical Specifications

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