MSP430F6433IPZ datasheet(21/119 Pages) TI1

21 / 119 page

MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433

www.ti.com

SLAS720D – AUGUST 2010 – REVISED DECEMBER 2015

Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1) (2)

TEMPERATURE (TA)

PARAMETER

VCC

PMMCOREVx

–40°C

25°C

60°C

85°C

UNIT

TYP

MAX

TYP

MAX

TYP

MAX

TYP

MAX

2.7

3.2

3.8

5.9

7.9

12.2

Low-power mode 3

ILPM3,

(LPM3) current, LCD 4-

2.7

3.2

6.1

8.1

LCD,

mux mode, internal

3 V

µA

2.8

3.3

6.2

8.3

int. bias

biasing, charge pump

disabled(3)(5)

2.8

3.3

4.9

6.4

8.4

13.7

3.8

2.2 V

3.9

µA

Low-power mode 3

4.0

(LPM3) current, LCD 4-

ILPM3

mux mode, internal

4.0

LCD,CP

biasing, charge pump

4.1

enabled(3)(6)

3 V

µA

4.2

(5)

LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump

disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz)

Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

(6)

LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump

enabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz)

Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

5.7

Thermal Resistance Characteristics

PARAMETER

VALUE

UNIT

QFP (PZ)

122

θJA

Junction-to-ambient thermal resistance, still air(1)

°C/W

BGA (ZQW)

108

QFP (PZ)

θJC(TOP)

Junction-to-case (top) thermal resistance(2)

°C/W

BGA (ZQW)

QFP (PZ)

θJB

Junction-to-board thermal resistance(3)

°C/W

BGA (ZQW)

(1)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

Specifications

Submit Documentation Feedback

Product Folder Links: MSP430F6438 MSP430F6436 MSP430F6435 MSP430F6433

MSP430F6433IPZ датащи(PDF) 21 Page - Texas Instruments

MSP430F6433IPZ датащи(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL