ISO7240CFDW datasheet(34/46 Pages) TI1

34 / 46 page

10 mils

40 mils

FR-4

r ~ 4.5

Keep this

space free

from planes,

traces, pads,

and vias

Ground plane

Power plane

Low-speed traces

High-speed traces

ISO7240CF, ISO7240C, ISO7240M

ISO7241C, ISO7241M, ISO7242C, ISO7242M

SLLS868R – SEPTEMBER 2007 – REVISED SEPTEMBER 2015

www.ti.com

11 Power Supply Recommendations

To ensure reliable operation at all data rates and supply voltages, a 0.1

μF bypass capacitor is recommended at

input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as

possible. If only a single primary-side power supply is available in an application, isolated power can be

generated for the secondary-side with the help of a transformer driver such as Texas Instruments SN6501 data

sheet . For such applications, detailed power supply design and transformer selection recommendations are

available in SN6501 data sheet (SLLSEA0).

12 Layout

12.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 28). Layer stacking should

be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency

signal layer.

•

Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

•

Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

•

Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100pF/in2.

•

Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the

stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the

power and ground plane of each power system can be placed closer together, thus increasing the high-frequency

bypass capacitance significantly. For detailed layout recommendations, see Application Note SLLA284, Digital

Isolator Design Guide.

12.1.1 PCB Material

For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of

up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the

requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower

dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-

extinguishing flammability-characteristics.

12.2 Layout Example

Figure 28. Recommended Layer Stack

Submit Documentation Feedback

Product Folder Links: ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M

ISO7240CFDW датащи(PDF) 34 Page - Texas Instruments

ISO7240CFDW датащи(HTML) 34 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

датащи скачать

ссылки URL