M95040-DRMF3TP datasheet(31/41 Pages) STMICROELECTRONICS

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M95040-A125 M95040-A145

DC and AC parameters

Table 14. AC characteristics

Symbol

Alt.

Parameter

Min. Max. Min. Max. Min. Max.

Unit

Test

conditions

specified in

Table 10

Test

conditions

specified in

Table 9 and

Table 10

Test

conditions

specified in

Table 11

fSCK Clock frequency

MHz

tSLCH

tCSS1 S active setup time

tSHCH

tCSS2 S not active setup time

tSHSL

tCS

S deselect time

tCHSH

tCSH S active hold time

tCHSL

S not active hold time

tCH(1)

tCLH Clock high time

tCL(1)

tCLL Clock low time

tCLCH(2)

tRC

Clock rise time

-2-2-2

µs

tCHCL(2)

tFC

Clock fall time

tDVCH

tDSU Data in setup time

tCHDX

tDH

Data in hold time

tHHCH

Clock low hold time after HOLD not active

tHLCH

Clock low hold time after HOLD active

tCLHL

Clock low set-up time before HOLD active

0-0-0

tCLHH

Clock low set-up time before HOLD not

active

0-0-0

tSHQZ(2)

tDIS

Output disable time

tCLQV(3)

Clock low to output valid

tCLQX

tHO

Output hold time

tQLQH(2)

tRO

Output rise time

tQHQL(2)

tFO

Output fall time

tHHQV

tLZ

HOLD high to output valid

tHLQZ(2)

tHZ

HOLD low to output high-Z

tWC

Write time

-4-4-4

1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).

2. Value guaranteed by characterization, not 100% tested in production.

3. tCLQV must be compatible with tCL (clock low time): if tSU is the Read setup time of the SPI bus master, tCL must be equal to

(or greater than) tCLQV+tSU.

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