M95040-DRMF3TP datasheet(25/41 Pages) STMICROELECTRONICS

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M95040-A125 M95040-A145

Application design recommendations

5.1

Supply voltage (VCC)

5.1.1

Operating supply voltage (VCC)

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Table 9 and Table 10).

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal Write cycle (tW). In order to

secure a stable DC supply voltage, it is recommended to decouple the VCC line with a

suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package

pins.

5.1.2

Power-up conditions

When the power supply is turned on, VCC continuously rises from VSS to VCC. During this

time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is

therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see

Figure 16).

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage

defined in Table 12 and Table 13.

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)

circuit is included.

At power-up, the device does not respond to any instruction until VCC reaches the internal

threshold voltage (this threshold is defined in the DC characteristics tables 12 and 13 as

VRES).

When VCC passes over the POR threshold, the device is reset and in the following state:

•

in the Standby power mode

•

deselected

•

Status register values:

–

Write Enable Latch (WEL) bit is reset to 0.

–

Write In Progress (WIP) bit is reset to 0.

–

BP1 and BP0 bits remain unchanged (non-volatile bits).

•

not in the Hold condition

As soon as the VCC voltage has reached a stable value within [VCC(min), VCC(max)] range,

the device is ready for operation.

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