L9959S datasheet(35/43 Pages) STMICROELECTRONICS

35 / 43 page

DocID023416 Rev 6

35/43

L9959S, L9959T

SPI functional description

Only the bits ‘CONFIG’ and ‘DIACLR’ in this register can be written, all other bits are ‘read-

only’

Table 33. Current Level (CONFIG_REG)

CL1

CL2

Current Level

Typical Current

No Change

5.0 A

3 (default value)

6.6 A

8.6 A

Table 34. Status and configuration register (STATCON_REG)

Bit

Name

CONFIG2

CONFIG1

CONFIG0

DIACLR2

DIACLR1

STATUS2

STATUS1

STATUS0

Bit

Name

Content

CONFIG2

VDD Test Threshold: 0: VDD Threshold Test is on 1: VDD Threshold test is off

CONFIG1

VDD Test Threshold 1:Lower VDD Test Threshold is lifted 0:Upper VDD Test Threshold is

lowered

CONFIG0

VDD Over-Voltage Latch: 0: Latch is disabled 1: Latch is enabled

DIACLR2

Reset DIA_REG2: 0: Reset errors in DIA_REG2 1: No action (Reading this bit always

returns „1.)

DIACLR1

Transfer Errors:

0: All latched errors of DIA_REG1 are transferred to DIA_REG2. DIA21,DIA20, DIA11,

DIA10are set to “1111”. During VS-Undervoltage DIACLR1 is disabled 1: No action

(Reading this bit always returns „1.)

STATUS2

Logic Level at Pin /ABE

STATUS1

VDD Under-Voltage: 0: Under-Voltage 1: No Under-Voltage

STATUS0

VDD Over-Voltage: 0: Over-Voltage

1: No Over-Voltage

This information is not reset during VS-Undervoltage. It will be reset by CONFIG0, SPI

reset or internal VDD reset

Reset(5.4.1)

POR

SPIR

ENDISR

DISR

RDR

L9959S датащи(PDF) 35 Page - STMicroelectronics

L9959S датащи(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

датащи скачать

ссылки URL