L9779WD datasheet(118/170 Pages) STMICROELECTRONICS

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Functional description

L9779WD

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DocID027452 Rev 5

Note:

The signal RST_PRL (partial reset) is active when RST_UV or SW_RST (Soft reset) is

active (straight by RST pin. It could be filtered by THOLD after the falling edge of the RST

and filtered by the crank event).

Access during a sequencer-run

A sequencer-run (which means the same as a monitoring cycle) is initiated by the writing of

a response (i.e. all answer bytes <RESP_BYTE3..0>) or a write to <RESPTIME> or by

reaching "end of time window". It must not be interrupted by a new access, i.e. the

monitoring module completes the action already started:



A sequencer-run was initiated by a "response write": The sequencer completes its task

with the data of the previous access and the new data are ignored.



A sequencer-run was initiated by a "response-time write": The sequencer uses the

response-time of the previous access, the error counter is correspondingly

incremented by one and the <CHRT> bit (REQUHI register) is set and the new data are

ignored. <CHRT> will be reset by reading and by the next start of a sequencer run (not

reset by the sequencer run that is started by a "response-time write"!)



A sequencer-run was initiated by "end of time window": The sequencer finishes the

started run, the error counter is incremented by one and the new data are ignored.

The writing of a response-time during a sequencer-run must not set the <CHRT> bit

(REQUHI register). The new response-time value is also not accepted. The writing of a

response during a sequencer-run must not set the <W_RESP> bit, the new response is also

not accepted.

Clock and time references

The monitoring module must work independently of the micro-controller clock so that it can

monitor the timing of the micro-controller. Therefore, a separate oscillator is necessary.

This oscillator is integrated in the L9779 and provides a clock CLK1 for the monitoring

module. Clocked with CLK1, a divider generates the base time of 101*1/f_clk = 101 *

1/64 kHz = 1.58 ms for the response-time and 8 * 101*1/64kHz =8* 1.58 ms = 12.6 ms for

the fixed time window. Accuracy of CLK1 is ±5% (or better).

The response-time is adjustable by the controller in the range 0ms to about 100ms (register

RESPTIME). The response-time can be calculated with the equation response-

time = (1+101*RESPTIME)*1/f_clk (where f_CLK depends on CONFIG6 bit1 value: if High -

default- f_clk = 64 kHz, if Low f_clk = 39 kHz).

The RESPTIME register is set to '0011 1111'b after a reset. The ERROR COUNTER is

incremented by one if the controller changes the response-time. If the response-time is set

to 0ms, then the ERROR COUNTER is incremented by one even if a correct response is

received within the time window. The maximum error reaction time is given by: maximum

response-time, response at the end of a time-window and ERROR COUNTER 0 ' 5 *

(100 ms + 12.6 ms) = 563 ms.

Note that clock-tolerances have to be taken into account additionally.

Maximum value: 0011 1111b

timer state

“000...00”

Table 54. Reset behaviour (continued)

Component:

Reset Condition:

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