L9779WD datasheet(115/170 Pages) STMICROELECTRONICS

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L9779WD

Functional description

169

Behaviour of AB1:

–

asynchronous reset to "0" with RST_UV

–

synchronous reset to "0" IF <WDA_INT> = '0' (EC < 5)

–

IF (AB1_CNT = 7) AND ((sequencer-run AND further error) OR soft-reset) THEN

AB1 = 1

ELSE unchanged.

Generation of a monitoring module reset

The monitoring module may cause a reset at the pin [RST] named "monitoring module

reset" in conjunction with the internal signal WD_RST. The generation of a monitoring

module reset depends on the state of the bit <INIT_WDR>.

<INIT_WDR> = '0' (reset state):

If <INIT_WDR> = '0', the signal <WD_RST> remains always inactive '0' and the monitoring

module can never generate a reset. The error counter can only be decremented via correct

responses. If <INIT_WDR> = '0' the state of the reset counter <RST_CNT> remains

unchanged when an ERROR COUNTER overflow occurs (description of the reset counter

<RST_CNT> see below).

<INIT_WDR> = '1':

If <INIT_WDR> = '1', an ERROR COUNTER overflow activates a reset [RST] (signal

<WD_RST> becomes active). The signal <WD_RST> becomes active (i.e. '1') due to an

ERROR COUNTER overflow when the value of the 3 bit reset counter <RST_CNT(2-0)> is

0..6. If the value of <RST_CNT> = "111" and an ERROR COUNTER overflow occurs

<WD_RST> remains inactive (i.e. '0') and no reset is generated.

The "reset counter" <RST_CNT> is incremented by one during a sequencer-run due to an

ERROR COUNTER overflow when <INIT_WDR> = '1' and <RST_CNT> is between 0 and

6. If <RST_CNT> = 7 and an ERROR COUNTER overflow occurs, the counter state

remains 7. The counter can not be decremented and can only reset to zero by an active

RST_UV signal.

The occurrence of a monitoring module reset is indicated via the flag <WDG_RST> = '1'.

Reading the flag via MSC clears it automatically.

In effect maximum 7 monitoring module resets can be generated between 2 active RST_UV

signal. (see also state table for <INIT_WDR> = '1' below).

The state of the "reset counter" <RST_CNT> can be read via MSC but cannot be changed.

In a factory test-mode the pin [WDA] is always active '0'; the internal signal <WDA_INT> is

not changed by the factory test-modes.

Table 51. State for <INIT_WDR> = 1

RST_CNT

old

“EC” > 7 and

sequencer-run

RST_CNT

new

WD_RST

000 .. 111

= RST_CNT old

‘0’, no monitoring module reset

000 .. 110

yes

= RST_CNT old + 1

‘1’, thus monitoring module reset

111

yes

= RST_CNT old =111

‘0’, no monitoring module reset

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