L9779WD datasheet(111/170 Pages) STMICROELECTRONICS

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L9779WD

Functional description

169

6.17.2

Monitoring module - WDA Functionality

Figure 73.

WDA block diagram

Each time the watchdog error counter is EC>7 the AB1-counter AB1_CNT increases. When

this counter is AB1_CNT=7 and a further error occurs, the after-run will be terminated. The

AB1-counter is not cleared when EC<7. AB1-counter is cleared when EC<5 and

<WDA_INT>='0', and is reset by RST_UV.

The monitoring module works independently of the controller functionality. The monitoring

module generates various questions, which the controller must fetch and correctly respond

to within a defined time window. The monitoring module checks whether the response is

returned in a time window and if the response is fully correct.

The question is a 4-bit word. This 4-bit word can be fetched by the controller using a read

access to register REQULO. The monitoring module also calculates the expected correct

response, which is compared to the actual response from the controller.

The response is a 32-bit word consisting of the 4 bytes RESP_BYTE3, RESP_BYTE2,

RESP_BYTE1 and RESP_BYTE0. The 4 bytes are sent to the monitoring module via MSC

in the order RESP_BYTE3 - RESP_BYTE2 - RESP_BYTE1 - RESP_BYTE0 using four

times the command WR_RESP - once for each answer byte.

Watchdog counters are always counting from power up onwards.

The monitoring cycle phase is initialized by (the end of) writing of RESP_BYTE0 (least

significant response byte) or by a write access to the RESPTIME register. The cycle starts

with a variable wait time (response time, set by register RESPTIME), followed by a fixed

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