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L6751B датащи(PDF) 32 Page - STMicroelectronics

номер детали L6751B
подробное описание детали  Digitally controlled dual PWM for Intel VR12 and AMD SVI
PDF  58 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L6751B датащи(HTML) 32 Page - STMicroelectronics

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Output voltage positioning
L6751B
32/58
Doc ID 024028 Rev 1
dence of the output voltage on the load current, a static error, proportional to the output cur-
rent, causes the output voltage to vary according to the sensed current.
Figure 7 shows the current sense circuit used to implement the load-line. The current flow-
ing across the inductor DCR is read through RSG. RSG programs a trans-conductance gain
and generates a current ISDROOP proportional to the current delivered by the single-phase
section that is then sourced from the SFB pin with proper gain eventually adjusted by the
PMBus commands. RSFB gives the final gain to program the desired load-line slope
(Figure 6).
The output characteristic vs. load current is then given by:
Equation 7
where RSLL is the resulting load-line resistance implemented by the single-phase section.
RSFB resistor can be then designed according to the RSLL as follows:
6.7
Dynamic VID transition support
The L6751B manages dynamic VID transitions that allow the output voltage of both sections
to be modified during normal device operation for power management purposes. OV, UV
and OC signals are masked during every DVID transition and they are re-activated with
proper delay to prevent from false triggering.
When changing dynamically the regulated voltage (DVID), the system needs to charge or
discharge the output capacitor accordingly. This means that an extra-current IDVID needs to
be delivered (especially when increasing the output regulated voltage) and it must be con-
sidered when setting the overcurrent threshold of both the sections. This current results:
Equation 8
where dVOUT / dTVID depends on the specific command issued (20 mV/μsec. for
SetVID_Fast and 5 mV/
μsec. for SetVID_Slow). Overcoming the total OC threshold during
the dynamic VID causes the device to latch and disable. Set proper filtering on ILIM to pre-
vent from false total-OC tripping.
As soon as the controller receives a new valid command to set the VID level for one (or
both) of the two sections, the reference of the involved section steps up or down according
to the target-VID with the programmed slope until the new code is reached. If a new valid
command is issued during the transition, the device updates the target-VID level and
performs the dynamic transition up to the new code. OV, UV are masked during the
transition and re-activated with proper delay after the end of the transition to prevent from
false triggering.
V
SOUT
VID
R
SFB
I
SDROOP
=
VID
R
SF B
DCR
R
SG
-------------
I
SOUT
VID
R
SLL
I
SOUT
=
⋅⋅
R
SFB
R
SLL
R
SG
DCR
-------------
=
I
DVID
C
OUT
dV
OUT
dT
VID
------------------
=



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