ADS5294IPFPR datasheet(7/81 Pages) TI1

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ADS5294

www.ti.com

SLAS776D – NOVEMBER 2011 – REVISED SEPTEMBER 2015

Pin Functions (continued)

DESCRIPTION

NAME

NO.

OUT1A_P, OUT1A_N

13, 14

Differential LVDS data output, wire 1, channel 1

OUT1B_P, OUT1B_N

15, 16

Differential LVDS data output, wire 2, channel 1

OUT2A_P, OUT2A_N

17, 18

Differential LVDS data output, wire 1, channel 2

OUT2B_P, OUT2B_N

19, 20

Differential LVDS data output, wire 2, channel 2

OUT3A_P, OUT3A_N

21, 22

Differential LVDS data output, wire 1, channel 3

OUT3B_P, OUT3B_N

23, 24

Differential LVDS data output, wire 2, channel 3

OUT4A_P, OUT4A_N

25, 26

Differential LVDS data output, wire 1, channel 4

OUT4B_P, OUT4B_N

27, 28

Differential LVDS data output, wire 2, channel 4

OUT5A_P, OUT5A_N

35, 36

Differential LVDS data output, wire 1, channel 5

OUT5B_P, OUT5B_N

33, 34

Differential LVDS data output, wire 2, channel 5

OUT6A_P, OUT6A_N

39, 40

Differential LVDS data output, wire 1, channel 6

OUT6B_P, OUT6B_N

37, 38

Differential LVDS data output, wire 2, channel 6

OUT7A_P, OUT7A_N

43, 44

Differential LVDS data output, wire 1, channel 7

OUT7B_P, OUT7B_N

41, 42

Differential LVDS data output, wire 2, channel 7

OUT8A_P, OUT8A_N

47, 48

Differential LVDS data output, wire 1, channel 8

OUT8B_P, OUT8B_N

45, 46

Differential LVDS data output, wire 2, channel 8

Power-down control input. Active High. The pin has an internal 220-k

Ω pulldown resistor.

Negative reference input and output. Internal reference mode: Reference bottom voltage (0.45 V) is output

REFB

on this pin. A decoupling capacitor is not required on this pin. External reference mode: Reference bottom

voltage (0.45 V) must be externally applied to this pin. Please see External Reference Mode of Operation.

Positive reference input and output. Internal reference mode: Reference top voltage (1.45 V) is output on this

REFT

pin. A decoupling capacitor is not required on this pin. External reference mode: Reference top voltage (1.45

V) must be externally applied to this pin. Please see External Reference Mode of Operation.

RESET

Active HIGH RESET input. The pin has an internal 220-k

Ω pulldown resistor.

SCLK

Serial clock input. The pin has an internal 220-k

Ω pulldown resistor.

SDATA

Serial data input. The pin has an internal 220-k

Ω pulldown resistor.

Serial data readout. This pin is in the high-impedance state after reset. When the <READOUT> bit is set, the

SDOUT

SDOUT pin becomes active. SDOUT is a CMOS digital output running from the AVDD supply.

CSZ

Serial enable chip select – active-low digital input

Input signal to synchronize channels and chips when used with reduced output data rates. If it is not used,

SYNC

add a

≤ 10-KΩ pulldown resistor.

LVDD

11, 49

Digital and I/O power supply, 1.8 V

LGND

12, 50

Digital ground

No Connection. Must leave floated

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