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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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USB3370 датащи(PDF) 8 Page - Microchip Technology |
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USB3370 датащи(HTML) 8 Page - Microchip Technology |
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8 / 75 page  USB3370 DS00001915B-page 8 2012 - 2015 Microchip Technology Inc. 17 RESETB Input, CMOS, Low When low, the part is suspended and the 3.3V and 1.8V regulators are disabled. When high, the USB3370 will operate as a normal ULPI device, as described in Section 5.6.2. The state of this pin may be changed asynchronously to the clock signals. When asserted for a minimum of 1 microsecond and then de-asserted, the ULPI registers are reset to their default state and all internal state machines are reset. 18 VDD18 Power N/A 1.8V Regulator Output. A 1.0uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB3370. 20 STP Input, CMOS High The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle. 19 DIR Output, CMOS N/A Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. 2 22 30 VDDIO Power N/A 1.8V to 3.3V ULPI interface supply voltage. FLAG 8 GND Ground N/A Ground. TABLE 2-1: USB3370 PIN DESCRIPTIONS (CONTINUED) Pin Name Direction/ Type Active Level Description |
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