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USB3370 датащи(PDF) 36 Page - Microchip Technology

номер детали USB3370
подробное описание детали  Enhanced Single Supply Hi-Speed USB ULPI Transceiver
PDF  75 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

USB3370 датащи(HTML) 36 Page - Microchip Technology

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USB3370
DS00001915B-page 36
2012 - 2015 Microchip Technology Inc.
6.2.2
ULPI REGISTER WRITE
A ULPI register write operation is given in Figure 6-3. The TX command with a register write DATA[7:6] = 10b is driven
by the Link at T0. The register address is encoded into DATA[5:0] of the TX CMD byte.
To write a register, the Link will wait until DIR is low, and at T0, drive the TX CMD on the data bus. At T2 the PHY will
drive NXT high. On the next rising clock edge, T3, the Link will write the register data. At T4, the PHY will accept the
register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data
packet. Finally, at T5, the PHY will latch the data into the register and the Link will pull STP low.
NXT
is used to throttle when the Link drives the register data on the bus. DIR is low throughout this transaction since
the PHY is receiving data from the Link. STP is used to end the transaction and data is registered after the de-assertion
of STP. After the write operation completes, the Link must drive a ULPI Idle (00h) on the data bus. If the databus is not
driven to idle the USB3370 may decode the non-zero bus value as an RX Command.
A ULPI extended register write operation is shown in Figure 6-4. To write an extended register, the Link will wait until
DIR
is low, and at T0, drive the TX CMD on the data bus. At T2 the PHY will drive NXT high. On the next clock T3 the
Link will drive the extended address. On the next rising clock edge, T4, the Link will write the register data. At T5, the
PHY will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal
the end of the data packet. At T5, the PHY will latch the data into the register. Finally, at T6, the Link will drive STP low.
Register Read
11b
XXXXXXb
Immediate Register Read Command where: DATA[5:0]
= 6-bit register address
101111b
Extended Register Read Command where the 8-bit
register address is available on the next cycle.
FIGURE 6-3:
ULPI REGISTER WRITE IN SYNCHRONOUS MODE
TABLE 6-2:
ULPI TX CMD BYTE ENCODING (CONTINUED)
Command Name
CMD Bits[7:6]
CMD Bits[5:0]
Command Description
DIR
CLK
DATA[7:0]
STP
NXT
TXD CMD
(reg write)
Idle
Reg Data[n]
Idle
ULPI Register
Reg Data [n-1]
Reg Data [n]
T0
T1
T2
T3
T5
T4
T6



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