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ADS5400IPZP датащи(PDF) 34 Page - Texas Instruments |
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ADS5400IPZP датащи(HTML) 34 Page - Texas Instruments |
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34 / 55 page ![]() ADS5400 SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016 www.ti.com Table 8. Serial Register 0x04 (Read or Write) Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0x04 Analog Offset Control bits<7:0> Defaults factory set BIT <7:0> Analog Offset control continued (least significant bits of 9-bit word) All 9-bits in this adjustment in address 0x03 and 0x04 set to 0 0000 0000 = –30 mV All 9-bits in this adjustment in address 0x03 and 0x04 set to 1 1111 1111 = 30 mV Step adjustment resolution is 120uV (or 1/4 LSB). Adjustments can be used for calibration of analog signal path offset (for instance offset error induced outside of the ADC) or to match multiple ADC offsets. The default setting for this register is factory set to provide ~0 mV of ADC offset in the output codes and is unique for each device. Performance of the ADC is not specified across the entire offset control range. Some performance degradation is expected as larger offsets are programmed. 34 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS5400 |
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