ADS5400IPZP datasheet(29/55 Pages) TI1

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ADS5400

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SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016

Device Functional Modes (continued)

In addition to CLKOUT alignment using RESET, a synchronization mode is provided in register 0x05. In this

mode, the OVR output becomes the SYNCOUT. The SYNCOUT will indicate which sample was present when

the RESET input pulse was captured in a HIGH state. The OVR indicator is not available when sync mode is

enabled. In single bus mode, only SYNCOUTA is used. In dual bus mode, only SYNCOUTB is used.

7.4.3 LVDS

Differential source loads of 100

Ω and 200Ω are provided internal to the ADS5400 and can be implemented using

values of 2.5, 4.5, and 5.5 mA are provided to save power or improve the LVDS signal quality when the

environment provides excessive loading.

7.5 Programming

7.5.1 Serial Interface

The serial port of the ADS5400 is a flexible serial interface which communicates with industry standard

microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the

operating modes of ADS5400. It is compatible with most synchronous transfer formats and can be configured as

a 3 or 4 pin interface in register 0x01h. In both configurations, SCLK is the serial interface input clock and

SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in and data

out. For 4 pin configuration, SDIO is data in only and SDO is data out only.

Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes,

depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle which

identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to

transfer the data. Table 1 indicates the function of each bit in the instruction cycle and is followed by a detailed

description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.

Table 1. Instruction Byte of the Serial Interface

MSB

LSB

Bit

Description

R/W

Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from ADS5400

and a low indicates a write operation to the ADS5400.

[N1:N0]

Identifies the number of data bytes to be transferred per Table 2. Data is transferred MSB first.

[A4:A0]

Identifies the address of the register to be accessed during the read or write operation. For multi-byte transfers, this

address is the starting address. Note that the address is written to the ADS5400 MSB first and counts down for each byte.

Table 2. Number of Transferred Bytes Within One

Communication Frame

Description

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

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