VDD

VDD

VDD

R = 125 W

Z = 50

o

W

Z = 50

o

W

R = 84 W

R = 84 W

R = 125 W

LVPECL

output

x_INP

x_INN

VDD

VDD

Clock generator:

VDD

Z + R = 50

o

s

W

R = 1 k W

R = 1 k W

R = 100 W

R = 100 W

C = 0.1 F

m

x_INP

x_INN

Z = 50

o

W

LVCMOS

output

R=50

from

measurement

equipment

W

+ VDDO/2

– VDDO/2

Z = 50

O

W

CDCLVC1310

SCAS917E – JULY 2011 – REVISED JANUARY 2014

www.ti.com

TEST CONFIGURATIONS

Figure 2 through Figure 8 illustrate how to set up the device for a variety of test configurations.

Figure 2. LVCMOS Output DC Configuration; Test Load Circuit

Figure 3. LVCMOS Input DC Configuration During Device Test

Figure 4. LVPECL Input Configuration During Device Test

10

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