TAS5548DCAR datasheet(49/116 Pages) TI1

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7-BitSlave Address

8-BitRegister Address(N)

8-BitRegisterDataFor

Address(N)

Start

Stop

SDA

SCL

8-BitRegisterDataFor

Address(N)

T0035-01

TAS5548

www.ti.com

SLES270A – NOVEMBER 2012 – REVISED APRIL 2015

Programming (continued)

The TAS5548 supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation

(400 kHz maximum). The TAS5548 performs all I2C operations without I2C wait cycles.

The I2C address is 0x36 if ASEL pin = '1, but if the value of the pin = '0', then respective values will be 0X34.

7.5.1.1 General I2C Operation

The I2C bus employs two signals—SDA (data) and SCL (clock)—to communicate between integrated circuits in a

system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte

(8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on SDA while the clock is high to indicate start and stop conditions. A high-to-low

transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must

occur within the low time of the clock period. These conditions are shown in Figure 40. The master generates the

7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an

acknowledge condition. The TAS5548 holds SDA low during the acknowledge clock period to indicate an

acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is

addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals

via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and

SCL signals to set the high level for the bus.

Figure 40. Typical I2C Sequence

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