PRELIMINARY
CY28324
Document #: 38-07002 Rev. *A
Page 2 of 23
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
X1
3
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
X2
4
O
Crystal Connection: Connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
REF0/MULTSEL0
48
I/O
Reference Clock 0/Current Multiplier Selection 0: 3.3V 14.318-MHz clock
output. This pin also serves as a power-on strap option to determine the current
multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as fol-
lows:
MULTSEL1:0
00 = IOH is 4 x IREF
01 = IOH is 5 x IREF
10 = IOH is 6 x IREF
11 = IOH is 7 x IREF
REF1/MULTSEL1
1
I/O
Reference Clock 1/Current Multiplier Selection 1: 3.3V 14.318-MHz clock
output. This pin also serves as a power-on strap option to determine the current
multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as fol-
lows:
MULTSEL1:0
00 = Ioh is 4 x IREF
01 = IOH is 5 x IREF
10 = IOH is 6 x IREF
11 = IOH is 7 x IREF
CPU0:1, CPU0:1#
41, 38, 40, 37
O
CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through the serial
input interface.
3VMREF/CPU_STP
#
45
I/O
Memory Reference Clock/CPU Output Control: The function of this pin is
controlled by the Mode input pin. When Mode input is sampled HIGH during
power-on reset, this pin will be configured as 3VMREF output. When Mode
input is sampled LOW during power-on reset, this pin will be configured as
CPU_STP# input.
3VMREF is a 3.3V output running at half the frequency of the CPU output clock.
CPU_STP# is a 3.3V LVTTL compatible input that disables CPU0, CPU0#,
CPU1 and CPU1# outputs.
3VMREF#/PCI_STP
#
44
I/O
Memory Reference Clock/PCI Output Control: The function of this pin is
controlled by the Mode input pin. When Mode input is sampled HIGH during
power-on reset, this pin will be configured as 3VMREF# output. When Mode
input is sampled LOW during power-on reset, this pin will be configured as
PCI_STP# input.
3VMREF# is a 3.3V output running at half the frequency of the CPU output
clock. 3VMREF# is 180 degree out of phase with respect to 3VMREF.
PCI_STP# is a 3.3V LVTTL-compatible input that disables PCI0:6 outputs.
3V66_0:3
31, 30, 28, 27
O
66-MHz Clock Outputs: 3.3V fixed 66-MHz clock.
PCI_F0/FS2
6
I/O
Free-running PCI Output 0/Frequency Select 2: 3.3V free-running PCI out-
put. This pin also serves as a power-on strap option to determine device op-
erating frequency as described in the Frequency Selection Table.
PCI_F1/FS3
7
I/O
Free-running PCI Output 1/Frequency Select 3: 3.3V free-running PCI out-
put. This pin also serves as a power-on strap option to determine device op-
erating frequency as described in the Frequency Selection Table.
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