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CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document #: 38-06052 Rev. *E
Page 16 of 19
Notes:
47. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
48. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Switching Waveforms (continued)
Interrupt Timing Diagrams
WRITE 1FFF (OR 1/3FFF)
tWC
Right Side Clears INTR:
tHA
READ 7FFF
tRC
tINR
WRITE 1FFE (OR 1/3FFE)
tWC
Right Side Sets INTL:
Left Side Sets INTR :
Left Side Clears INT L:
READ 7FFE
tINR
tRC
ADDRESSR
CE L
R/W L
INT L
OE L
ADDRESSR
R/WR
CE R
INTL
ADDRESSR
CER
R/WR
INTR
OE R
ADDRESSL
R/WL
CE L
INTR
tINS
tHA
tINS
(OR 1/3FFF)
OR 1/3FFE)
[47]
[48]
[48]
[48]
[47]
[48]