ATmega16 datasheet(205/315 Pages) ATMEL

205 / 315 page

205

ATmega16(L)

2466E–AVR–10/02

If Auto Triggering is used, the exact time of the triggering event can be indeterministic.

Special care must be taken when updating the ADMUX Register, in order to control

which conversion will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If

the ADMUX register is changed in this period, the user cannot tell if the next conversion

is based on the old or the new settings. ADMUX can be safely updated in the following

ways:

When ADATE or ADEN is cleared.

During conversion, minimum one ADC clock cycle after the trigger event.

After a conversion, before the interrupt flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next

ADC conversion.

Special care should be taken when changing differential channels. Once a differential

channel has been selected, the gain stage may take as much as 125 µs to stabilize to

the new value. Thus conversions should not be started within the first 125 µs after

selecting a new differential channel. Alternatively, conversion results obtained within this

period should be discarded.

The same settling time should be observed for the first differential conversion after

changing ADC reference (by changing the REFS1:0 bits in ADMUX).

The settling time and gain stage bandwidth is independent of the ADHSM bit setting.

ADC Input Channels

When changing channel selections, the user should observe the following guidelines to

ensure that the correct channel is selected:

In Single Conversion mode, always select the channel before starting the conversion.

The channel selection may be changed one ADC clock cycle after writing one to ADSC.

However, the simplest method is to wait for the conversion to complete before changing

the channel selection.

In Free Running mode, always select the channel before starting the first conversion.

The channel selection may be changed one ADC clock cycle after writing one to ADSC.

However, the simplest method is to wait for the first conversion to complete, and then

change the channel selection. Since the next conversion has already started automati-

cally, the next result will reflect the previous channel selection. Subsequent conversions

will reflect the new channel selection.

When switching to a differential gain channel, the first conversion result may have a

poor accuracy due to the required settling time for the automatic offset cancellation cir-

cuitry. The user should preferably disregard the first conversion result.

ADC Voltage Reference

The reference voltage for the ADC (VREF) indicates the conversion range for the ADC.

Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be

selected as either AVCC, internal 2.56V reference, or external AREF pin.

AVCC is connected to the ADC through a passive switch. The internal 2.56V reference

is generated from the internal bandgap reference (VBG) through an internal amplifier. In

either case, the external AREF pin is directly connected to the ADC, and the reference

voltage can be made more immune to noise by connecting a capacitor between the

AREF pin and ground. VREF can also be measured at the AREF pin with a high impedant

voltmeter. Note that VREF is a high impedant source, and only a capacitive load should

be connected in a system.

ATMEGA16 датащи(PDF) 205 Page - ATMEL Corporation

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