LMV712TL datasheet(13/24 Pages) TI1

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TIME (2µs/div)

LMV712-N, LMV712-N-Q1

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SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014

Figure 33.

A glitch-free output waveform is highly desirable in many applications, one of which is power amplifier control

loops. In this application, the LMV712-N is used to drive the power amplifier's power control. If the LMV712-N did

not have a smooth output ramp during turn on, it would directly cause the power amplifier to produce a glitch at

its output. This adversely affects the performance of the system.

To enable the amplifier, the shutdown pin must be pulled high. It should not be left floating in the event that any

leakage current may inadvertently turn off the amplifier.

Printed Circuit Board Consideration

To properly bypass the power supply, several locations on a printed circuit board need to be considered. A 6.8µF

or greater tantalum capacitor should be placed at the point where the power supply for the amplifier is introduced

onto the board. Another 0.1µF ceramic capacitor should be placed as close as possible to the power supply pin

of the amplifier. If the amplifier is operated in a single power supply, only the V+ pin needs to be bypassed with a

0.1µF capacitor. If the amplifier is operated in a dual power supply, both V+ and V− pins need to be bypassed.

It is good practice to use a ground plane on a printed circuit board to provide all components with a low inductive

ground connection.

Surface mount components in 0805 size or smaller are recommended in the LMV712-N application circuits.

Designers can take advantage of the DSBGA, VSSOP and WSON miniature sizes to condense board layout in

order to save space and reduce stray capacitance.

Capacitive Load Tolerance

The LMV712-N can directly drive 200pF in unity-gain without oscillation. The unity-gain follower is the most

sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase margin of amplifiers.

The combination of the amplifier's output impedance and the capacitive load induces phase lag. This results in

either an under-damped pulse response or oscillation. To drive a heavier capacitive load, Figure 34 can be used.

Figure 34.

In Figure 34, the isolation resistor RISO and the load capacitor CL form a pole to increase stability by adding more

phase margin to the overall system. The desired performance depends on the value of RISO. The bigger the RISO

resistor value, the more stable VOUT will be. But the DC accuracy is degraded when the RISO gets bigger. If there

were a load resistor in Figure 34, the output voltage would be divided by RISO and the load resistor.

Product Folder Links: LMV712-N LMV712-N-Q1

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