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Z86L7208FSC датащи(PDF) 24 Page - Zilog, Inc. |
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Z86L7208FSC датащи(HTML) 24 Page - Zilog, Inc. |
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24 / 71 page ![]() Z86C72/C92/L72/L92 IR Microcontroller Zilog 6-24 P R E L I M I N A R Y DS97LVO0900 PIN FUNCTIONS (Continued) Port 1 (P17-P10). Port 1 is a multiplexed Address (A7-A0) and Data (D7-D0), CMOS compatible port. Port 1 is dedi- cated to the Zilog ZBus®-compatible memory interface. The operations of Port 1 are supported by the Address Strobe (/AS) and Data Strobe (/DS) lines, and by the Read/Write (R//W) and Data Memory (/DM) control lines. Data memory read/write operations are done through this port (Figure 12). If more than 256 external locations are re- quired, Port 0 outputs the additional lines. Port 1 can be placed in the high-impedance state along with Port 0, /AS, /DS, and R//W, allowing the Z86L/CX2 to share common resources in multiprocessor and DMA ap- plications. Port1 can also be configured for standard port output mode. Figure 12. Port 1 Configuration Port 1 (I/O or AD7 - AD0) Optional Handshake Controls /DAV1 and RDY1 (P33 and P34) Z86LXX MCU 8 OEN Out In PAD Auto Latch R ≈ 500 KΩ |
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