LM76 datasheet(5/22 Pages) TI

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LM76

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SNIS109E – JANUARY 2000 – REVISED MARCH 2013

Logic Electrical Characteristics

DIGITAL DC CHARACTERISTICS Unless otherwise noted, these specifications apply for +VS = +5.0 Vdc ±10% for the

LM76CHM-5. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted.

Typical(1)

Limits(2)

Units

Symbol

Parameter

Conditions

(Limit)

+VS × 0.7

V (min)

SDA and SCL Logical “1” Input

VIN(1)

Voltage

+VS+0.3

V (max)

−0.3

V (min)

SDA and SCL Logical “0” Input

VIN(0)

Voltage

+VS × 0.3

V (max)

VIN(HYST)

SDA and SCL Digital Input Hysteresis

500

250

mV (min)

2.0

V (min)

VIN(1)

A0 and A1 Logical “1” Input Voltage

+VS+0.3

V (max)

−0.3

V (min)

VIN(0)

A0 and A1 Logical “0” Input Voltage

0.8

V (max)

IIN(1)

Logical “1” Input Current

VIN = + VS

0.005

1.0

μA (max)

IIN(0)

Logical “0” Input Current

VIN = 0V

−0.005

−1.0

μA (max)

CIN

Capacitance of All Digital Inputs

IOH

High Level Output Current

VOH = + VS

μA (max)

VOL

Low Level Output Voltage

IOL = 3 mA

0.4

V (max)

T_CRIT_A Output Saturation Voltage

IOUT = 4.0 mA

(3)

0.8

V (max)

Conversions

T_CRIT_A Delay

(max)

CL = 400 pF

tOF

Output Fall Time

250

ns (max)

IO = 3 mA

(1)

Typicals are at TA = 25°C and represent most likely parametric norm.

(2)

Limits are ensured to AOQL (Average Outgoing Quality Level).

(3)

For best accuracy, minimize output loading. Higher sink currents can affect sensor accuracy with internal heating. This can cause an

error of 0.64°C at full rated sink current and saturation voltage based on junction-to-ambient thermal resistance.

SERIAL BUS DIGITAL SWITCHING CHARACTERISTICS Unless otherwise noted, these specifications apply for +VS = +5.0

Vdc ±10% for the LM76CHM-5, CL (load capacitance) on output lines = 80 pF unless otherwise specified. Boldface limits

apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted.

Typical(1)

Limits(2)(3)

Units

Symbol

Parameter

Conditions

(Limit)

SCL (Clock) Period

2.5

μs(min)

Data in Set-Up Time to SCL High

100

ns(min)

Data Out Stable after SCL Low

ns(min)

SDA Low Set-Up Time to SCL Low (Start Condition)

100

ns(min)

SDA High Hold Time after SCL High (Stop Condition)

100

ns(min)

(1)

Typicals are at TA = 25°C and represent most likely parametric norm.

(2)

Limits are ensured to AOQL (Average Outgoing Quality Level).

(3)

Timing specifications are tested at the bus input logic levels (Vin(0)=0.3xVA for a falling edge and Vin(1)=0.7xVA for a rising edge) when

the SCL and SDA edge rates are similar.

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