VP5313/VP5513

14

10.250

µs

48 IRE

10.500

µs

6.5D (12.910

µs)

2.0D (3.972

µs)

1.0D (1.986

µs)

16.0D (31.778

µs)

32.0D (63.556)

0.240

µs

50 IRE

0 IRE

0 IRE

48 IRE

50 IRE

10.750

µs

0.288

µs

52 IRE

2 IRE

52 IRE

Encoder minimum

Encoder nominal

Encoder maximum

Description

H-sync to clock run-in

Clock run-in maximum

Clock run-in minimum

Data bit differential (high - low)

Clock run-in differential (max. - min)

Interval

A

B

C

D

E

H

Table. 5 Closed Caption data timing. (source EIA R - 4.3 Sept 16 1992)

Notes

1.

The Horizontal line frequency fH is nominally 15734.26Hz ±0.05Hz. Interval D shall be adjusted to D = 1/(fH x 32) for the

instantaneous fH at line 21.

2.

The clock run-in signal consists of 7.0 cycles of a 0.5034965MHz (1/D) sine wave when measured from the leading to trailing

0 IRE points. The sine wave is to be symmetrical about the 25 IRE level.

3.

The negative going midpoints (half amplitude) of the clock run-in shall be coherent with the midpoints (half amplitude) of the

Start and Data bit transitions.

4.

Two characters, each consisting of 7 data bits and 1 odd parity bit.

5.

2 T Bar, measured between the 10% and 90% amplitude points.

6.

The clock run-in maximum level shall not differ from the data bit high level by more than

±1 IRE. The clock run-in minimum

level shall not differ from the data bit low level by more than

±1 IRE.