0AMA datasheet(15/23 Pages) MITEL

15 / 23 page

PDSP16510A MA

DAV output will not asynchronously go active as happens in a

single device system. Instead DAV will only go active when

DEN eventually goes active. Since DEN is the inverted DAV

output from a previous device, it is thus never possible for two

devices to be actively outputing data. The DAV active going

edge remains synchronised to the DOS strobe since the DEN

input will only go active when a previous DAV goes in-active.

A further change to the output circuitry ensures that the output

buffer is primed even though DEN is not active. The first word,

however, only progresses as far as the final output latch. The

output bus is not enabled, and address increments do not

occur, until DEN is finally received. This modification to the

internal control logic ensures that the output buffer does not

impose unnecessary gaps between consecutive transforms.

These gaps would, in turn, force the required DOS frequency

to be greater than the DIS frequency ( or greater than twice or

four times the frequency with 50% and 75% overlaps ).

The system illustrated by Figure 9 produces a common

DAV output by OR'ing together all the individual, active low,

DAV outputs. This is not guaranteed to give an indication when

one transform has finished, and the next one has started,

since it may simply glitch as one DAV goes in-active and the

next one goes active after some delay. This glitch will not

cause system problems since it occurs at a point clear of the

high going edge of the DOS strobe. To provide a marker for

the end of a transform each in-active going DAV edge should

set its own latch, which is then reset by a subsequent DOS

edge. The output of the latches can then be OR'd together if

necessary.

Three multiple device operating modes are actually pro-

vided, and are selected with Control Register Bits 10:9. The

choice of a particular mode is application dependent, and will

effect the maximum sampling rate achievable with a given

number of devices.

MULTIPLE DEVICE SAMPLING RATES

MODE 1. (BITS 10:9 = 01)

In this mode transfers in and out of the device are concurrent

with transform operations. This mode must not be used for

1024 point transforms due to internal memory size restric-

tions. When real transforms are performed in this mode, only

the real data input is used, regardless of the amount of block

overlapping.

The increase in performance is directly related to the

number of devices provided, but the input and output rates are

limited to FØ where F and Ø are as defined previously. Within

this restriction the theoretical performance is given by;

NnS > PK+4W, or 0.5NnS > PK+4W, or 0.25NnS > PK+4W

for 0%, 50%, or 75% overlapping. N is the number of devices,

n is the transform size, S is the DIS strobe period, P is the

number of system clock periods given in Table 4, K is the

system clock period, and W is the DOS strobe period.

If an output processor is provided for every device, two

devices with 50% block overlapping or four devices with 75%

block overlapping will give the same sampling rates as a single

device with no overlapping. If only one output processor is

provided, the two or four times increase needed in the output

rate over the input rate, usually imposes a limit on the input

rate, since the output rate is limited to a factor, F, of the system

clock.

In this operating mode the DIS and DOS strobes can

often be tied together, since a faster DOS strobe gives no

improvement in the sampling rates possible. This remains true

even when the output rate must be twice or four times the input

rate due to block overlapping. Options can then be used which

internally divide the DIS strobe by two or four, and thus allow

the input to be driven by the faster DOS strobe.

In this mode the LFLG goes in-active after 25%, 50%, or

100% of the block has been loaded. When multiple transforms

are performed concurrently (for example 4 x 64) a LFLG

transition occurs at the relevant point whilst the first block in

the group is being loaded. LFLG then goes high again and

returns low at the overlap point in the last block. This double

LFLG transition allows two devices to support 50% block

overlapping, since the first transition from the first device can

be used to initiate the load procedure in the second device.

The second transition from the second device then initiates a

new load procedure in the first device. The additional edges

from each device have no effect since they occur when the

device they are driving is already doing a load operation.

In such a two device system supporting 50% overlaps the

inverted DAV from the first device must drive the DEN input of

the second device. The data dumping time is then shared

equally between both devices. The second device only out-

puts data when the first has finished, but both dumps must be

finished in the time taken to load the group of blocks if only one

output processor is provided. Without the DAV/DEN connec-

tion one device would only have had the time needed to load

half of one sub block in which to dump its data.

In a similar manner four devices will handle 75% overlaps

when concurrent multiple transforms are to be computed. The

second, third, and fourth devices make use of the first transi-

tion, and ignore the second. The first device uses the second

transition from the last device, and ignores the first. With the

DAV/DEN connection each device will have one quarter of the

load time to dump its data when a single output processor is

provided .

More than two devices will provide increased perform-

ance for multiple transforms with 50% overlapping, and more

than four devices will increase the performance with 75%

overlapping. External logic is then needed to ensure that each

device only uses the correct LFLG transition. Any device

should only use the negative LFLG transition from a previous

device if its own LFLG is low, and the LFLG output from the

previous device plus one is low.

MODE 2 (BITS 10:9 = 10)

This mode is suitable for all transform sizes, since separate

load, transform, and then dump operations occur. More de-

vices than required by Mode 1 are necessary to achieve a

given sampling rate, but the input and output rates can be any

value up to the full system clock rate with the A grade part. As

with Mode 1, additional output processors are needed to

avoid the sampling rate restriction imposed by block overlap-

ping.

The number of devices, N, needed to achieve a given

sample rate can be derived from the following formula:

NnS > nS + PK + D for no overlapping

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