PDSP16256AC datasheet(19/28 Pages) MITEL

19 / 28 page

PDSP16256

Control Register

The internal operation of the PDSP16256 is

controlled by the status of a 16-bit control register. In

the dual filter modes both networks are controlled by

the same register. The significance of the various

bits are shown in Table 6. Tables 7 and 8 define the

control register bit interdependence for the filter and

bank swapping modes.

The control register is double buffered. This allows

the writing of a new control word without affecting the

current operation of the device. To activate the new

control register after it has been written to the device

the bank swap signal must be toggled. After a reset

the active control register is loaded directly and bank

swap need not be used.

Control

Function

Bits

765

Control by input pin

Lower bank selected

Upper bank selected

Swap on every sample clock

Bits

Decode

Function

Dual filter mode

Single filter mode

14:13

Sample rate is the system clock

14:13

Sample rate is half the system clock

14:13

Sample rate is quarter the system

clock

14:13

Sample rate is eighth the system clock

Output rate equals the input rate

Decimate-by-two

11:10

Intermediate device

11:10

Interface device

11:10

Termination device

11:10

Single device

9:8

These bits MUST be at logical zero

Bank swap is controlled by input pin

Bank swap is controlled by Bit 6

Lower bank if bit 7 is set

Upper bank if bit 7 is set

This bit must be at logical zero

Two independent filters

Two filters in cascade

3:0

These bits MUST be at logical zero

Control

Function

Bits

Two independent filters

Two filters in cascade

Single Filter

Table 8 Control register bank swap bits

Table 7 Control register filter mode bits

Table 6 Control register bit allocation

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