PDSP16256AC datasheet(9/28 Pages) MITEL

9 / 28 page

PDSP16256

Dual Indipendant Filter Options

When operating as two independent filters the device

accepts 16 bit data on both the DA and DB buses at the

selected sample rate, see Fig. 8. Results are available

from both the F and X buses. The F bus may be tristated

using the OEN input. Signal OEN is registered onto the

device and does not therefore take effect until the first

SCLK rising edge

Each filter must be configured in the same manner, and

multiple device expansion is not possible due to the pin

re-organization. The latter requirement can, of course,

still be satisfied by several devices configured as single

filters.

Dual independent filter mode is selected by setting

control register bits 15 and 4 to a zero. The required filter

length is selected using control register bits 14 and 13 as

summarised in Table 4, which also shows the resulting

latency. As in single filter mode normal or decimate-by-

two operation can be selected using control register bit

12.

Dual Cascaded Filter Options

When operating as two cascaded filters the device ac-

cepts 16 bit data on the DA bus at the selected sample

rate. Results are presented on the 32-bit X bus, see Fig.

9. Each filter must be configured in the same manner.

Multiple device expansion is not possible in this mode.

Dual cascaded filter mode is selected by setting control

filter length is selected using control register bits 14 and

13 as summarised in Table 4, which also shows the

resulting latency. The decimate-by-two option is not

available in this mode.

The data for the second filter network is extracted as the

middle 16 bits from the first networks accumulated result.

For successful operation the first filter network must have

unity gain. See the section on filter accuracy for more

details.

The cascade option is used to increase the stop band

rejection in a practical filter application. Theoretically,

increasing the number of taps in an FIR filter will increase

the stop band rejection, but this assumes floating point

calculations with no accuracy limitations. In practice, with

fixed point arithmetic, better performance is achieved

with two smaller filters in series.

Input

Output

Filter

Setup

14 13 12

Rate

Length

Latency

Ind

Cas

0 0 0

SCLK

8 Taps

0 0 1

SCLK

SCLK/2

16 Taps

0 1 0 SCLK/2

SCLK/2

16 Taps

0 1 1 SCLK/2

SCLK/4

32 Taps

1 0 0 SCLK/4

SCLK/4

32 Taps

1 0 1 SCLK/4

SCLK/8

64 Taps

1 1 0 SCLK/8

SCLK/8

64 Taps

Table 4. Dual Filter options

Figure. 9 Dual cascaded filter bus utilisation

Figure. 8 Dual independent filter bus utilisation

DA15:0

F31:0

OEN

NETWORK

DUAL

MODE

SINGLE

MODE

MUX

DB15:0

X31:0

DA15:0

F31:0

OEN

NETWORK

DUAL

MODE

SINGLE

MODE

MUX

DB15:0

X31:0

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