SM5847AF

NIPPON PRECISION CIRCUITS—19

Audio Data Input (INF1N, DI/INF2N, IW1N/DIL, IW2N/DIR, BCKI, LRCI)

The input data format and input pin functions are

selected by the state of INF1N and INF2N. When

INF1N is LOW, the inputs are left and right-channel

data inputs, and when INF1N is HIGH, the

DI/INF2N input is an input format select pin, and

DIL and DIR are the audio data inputs.

Input data format select

Input data word length

The input data word length is selected by the state of

IW1N and IW2N when INF1N is LOW. 20-bit is

selected when INF1N is HIGH.

Jitter-free Function (SYNCN)

The arithmetic circuit and output control timing is

derived from the system clock, and is therefore inde-

pendent of the input LRCI and BCKI clocks.

Accordingly, any jitter in the data input clock (LRCI

and BCKI) does not cause jitter in the output.

Generally, the internal timing is synchronized to the

LRCI input timing after a system reset release, when

RSTN goes from LOW to HIGH, on the first LRCI

clock start edge. If the input timing and LRCI start

edge timing subsequently drift, the input timing is

automatically resynchronized when the timing error

exceeds a certain value. There are 2 timing error val-

ues at which resynchronization occurs, selected by

the state of SYNCN.

Jitter-free mode (SYNCN = HIGH)

When SYNCN is HIGH, the timing error value is

±3/8

× (LRCI clock period). When the difference

between the input timing and LRCI start edge posi-

tion do not exceed this value, internal timing is not

resynchronized and all functions continue to operate

normally.

Sync mode (SYNCN = LOW)

When SYNCN is LOW, the timing error value is ±1

× (XTI master clock period), which is a much

smaller timing error tolerance than in jitter-free

mode. In this mode, the internal timing is guaranteed

to follow the LRCI clock timing within this toler-

ance, making this mode useful for systems con-

structed from a multiple number of SM5847AF

devices.

Table 7. Input settings and functions

INF1N

DI/INF2N

Input fo r m a t

Pin function selection

DI/INF2N

IW1N/DIL

IW2N/DIR

LO W

−

1. Alternating left-channel and right-channel data input on a single input DI.

DI

IW1N

IW2N

LO W

−

HIGH

L O W

LR alternating, left-justified data

INF2N

DIL

DIR

HIGH

HIGH

2. S i m ultaneous left-channel and right-channel data input on two inputs, DIL and DIR, respectively.

Table 8. Input data word length select

INF1N

IW1N/DIL

IW2N/DIR

Input word length

LO W

L O W

L O W

24 bits

HIGH

L O W

20 bits

L O W

HIGH

18 bits

HIGH

HIGH

16 bits

HIGH

–

–

24 bits