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SM5847AF датащи(PDF) 18 Page - Nippon Precision Circuits Inc

номер детали SM5847AF
подробное описание детали  High-fidelity Digital Audio, Multi-function Digital Filter
PDF  30 Pages
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производитель  NPC [Nippon Precision Circuits Inc]
домашняя страница  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM5847AF датащи(HTML) 18 Page - Nippon Precision Circuits Inc

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SM5847AF
NIPPON PRECISION CIRCUITS—18
System Reset (RSTN)
During normal device operation, reset signals are not
required. However, the SM5847AF must be reset
under the following conditions.
s
At power-ON
s
When the LRCI clock and internal operation tim-
ing need to be resynchronized in jitter-free mode.
s
After the LRCI or XTI clocks, or both, stop and
are subsequently started.
The system is reset by applying a LOW-level pulse
on RSTN.
When RSTN is LOW, the DOL and DOR outputs are
tied LOW, muting the output signal to an attenuation
level of
−∞.
After system reset, when RSTN goes HIGH, the
arithmetic and output timing counters are reset on
the first LRCI start edge, assuming that the XTI and
LRCI input clocks have already stabilized. The LRCI
start edge is determined by the state of INF1N and
INF2N. When INF1N is LOW or when both INF1N
and INF2N are HIGH, the start edge is the rising
edge. When INF1N is HIGH and INF2N is LOW, the
start edge is the falling edge.
Table 6. Master clock frequency example
Sampling
frequency
fs (kHz)
XTI system clock frequency (MHz)
CKSLN = HIGH (192fs)
CKSLN = LOW (256fs)
CKD V 1
CKD V 2
CKD V 1
CKD V 2
CKD V 1
CKD V 2
CKD V 1
CKD V 2
CKD V 1
CKD V 2
CKD V 1
CKD V 2
L O W
L O W
HIGH
HIGH
HIGH
L O W
L O W
L O W
HIGH
HIGH
HIGH
L O W
192fs
384fs
768fs
256fs
512fs
1024fs
3 2
6.144
12.288
24.576
8.192
16.384
32.768
44.1
8.4627
16.9344
33.8688
11.2896
22.5792
45.1584
4 8
9.216
18.432
36.864
12.288
24.576
49.152
88.2
16.9344
33.8688
Not guaranteed1
1. Refer to the AC characteristics system clock ratings.
22.5792
45.1584
Not guaranteed
9 6
18.432
36.864
Not guaranteed
24.576
49.152
Not guaranteed
176.4
33.8688
Not guaranteed
Not guaranteed
Not guaranteed
Not guaranteed
Not guaranteed
1 9 2
36.864
Not guaranteed
Not guaranteed1
Not guaranteed
Not guaranteed
Not guaranteed
Figure 5. System reset timing and output muting (INF1N = LOW or INF1N = INF2N = HIGH)
LRCI
RSTN
WCKO
OMD=H
8fs
RSTN=L
OMD=L
4fs
DOL/DOR
zero
Internal reset



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