Maximum Duty Cycle =

2

1

RT =

x 6.25 x 10

9

1

¨

©

§

- 110 ns

LM5035A

www.ti.com

SNVS537F – JANUARY 2008 – REVISED APRIL 2013

Oscillator, Sync Capability

The LM5035A oscillator frequency is set by a single external resistor connected between the RT and AGND pins.

To set a desired oscillator frequency, the necessary RT resistor is calculated from:

(2)

For example, if the desired oscillator frequency is 400kHz (HO and LO each switching at 200 kHz) a 15 k

Ω

resistor would be the nearest standard one percent value.

Each output (HO, LO, SR1 and SR2) switches at half the oscillator frequency. The voltage at the RT pin is

internally regulated to a nominal 2V. The RT resistor should be located as close as possible to the IC, and

connected directly to the pins (RT and AGND). The tolerance of the external resistor, and the frequency

tolerance indicated in the Electrical Characteristics, must be taken into account when determining the worst case

frequency range.

The LM5035A can be synchronized to an external clock by applying a narrow pulse to the RT pin. The external

clock must be at least 10% higher than the free-running oscillator frequency set by the RT resistor. If the external

clock frequency is less than the RT resistor programmed frequency, the LM5035A will ignore the synchronizing

pulses. The synchronization pulse width at the RT pin must be a minimum of 15 ns wide. The clock signal should

be coupled into the RT pin through a 100 pF capacitor or a value small enough to ensure the pulse width at RT

is less than 60% of the clock period under all conditions. When the synchronizing pulse transitions low-to-high

(rising edge), the voltage at the RT pin must be driven to exceed 3.2V volts from its nominal 2 VDC level. During

the clock signal’s low time, the voltage at the RT pin will be clamped at 2 VDC by an internal regulator. The

output impedance of the RT regulator is approximately 100

Ω. The RT resistor is always required, whether the

oscillator is free running or externally synchronized.

Gate Driver Outputs (HO & LO)

The LM5035A provides two alternating gate driver outputs, the floating high side gate driver HO and the ground

referenced low side driver LO. Each driver is capable of sourcing 1.25A and sinking 2A peak. The HO and LO

outputs operate in an alternating manner, at one-half the internal oscillator frequency. The LO driver is powered

directly by the VCC regulator. The HO gate driver is powered from a bootstrap capacitor connected between HB

and HS. An external diode connected between VCC (anode pin) and HB (cathode pin) provides the high side

gate driver power by charging the bootstrap capacitor from VCC when the switch node (HS pin) is low. When the

voltage.

The HB and VCC capacitors should be placed close to the pins of the LM5035A to minimize voltage transients

due to parasitic inductances since the peak current sourced to the MOSFET gates can exceed 1.25A. The

recommended value of the HB capacitor is 0.01 µF or greater. A low ESR / ESL capacitor, such as a surface

mount ceramic, should be used to prevent voltage droop during the HO transitions.

The maximum duty cycle for each output is limited to slightly less than 50% due to the internally fixed deadtime

and any programmed sync rectifier delay. The typical deadtime in this condition is 70 ns. The programmed sync

rectifier delay is determined by the DLY pin resistor. If the COMP pin is open circuit, the outputs will operate at

maximum duty cycle. The maximum duty cycle for each output can be calculated with the following equation:

(3)

and T1 is the programmed sync rectifier delay. For example, if the oscillator frequency is 200 kHz, each output

duty cycle at this frequency is calculated to be 49.3%. Using a programmed sync rectifier delay of 100 ns, the

maximum duty cycle is reduced to 48.3%.

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