LM5035AMHXSLASHNOPB datasheet(4/40 Pages) TI

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LM5035A

SNVS537F – JANUARY 2008 – REVISED APRIL 2013

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Pin Descriptions for LM5035A and LM5035A–1

HTSSOP 20

WQFN PIN

HTSSOP 28

Name

Description

Application Information

PIN LM5035A

LM5035A

PIN LM5035A-1

RAMP

Modulator ramp signal

An external RC circuit from VIN sets the

ramp slope. This pin is discharged at the

conclusion of every cycle by an internal

FET. Discharge is initiated by either the

internal clock or the Volt • Second clamp

comparator.

UVLO

Line Under-Voltage Lockout An external voltage divider from the

power source sets the shutdown and

standby comparator levels. When UVLO

reaches the 0.4V threshold the VCC and

REF regulators are enabled. When

UVLO reaches the 1.25V threshold, the

SS pin is released and the device enters

the active mode. Hysteresis is set by an

internal current sink that pulls 23 µA

from the external resistor divider.

OVP

Line Over-Voltage

An external voltage divider from the

Protection

power source sets the shutdown levels.

The threshold is 1.25V. Hysteresis is set

by an internal current source that

sources 23µA into the external resistor

divider.

COMP

Input to the Pulse Width

An external opto-coupler connected to

Modulator

the COMP pin sources current into an

internal NPN current mirror. The PWM

duty cycle is maximum with zero input

current, while 1mA reduces the duty

cycle to zero. The current mirror

improves the frequency response by

reducing the AC voltage across the

opto-coupler detector.

Oscillator Frequency

Normally biased at 2V. An external

Control and Sync Clock

resistor connected between RT and

Input

AGND sets the internal oscillator

frequency. The internal oscillator can be

synchronized to an external clock with a

frequency higher than the free running

frequency set by the RT resistor.

AGND

Analog Ground

Connect directly to Power Ground.

Current Sense input for

If CS exceeds 0.25V, the output pulse

current limit

will be terminated, entering cycle-by-

cycle current limit. An internal switch

holds CS low for 50ns after HO or LO

switches high to blank leading edge

transients.

Soft-start Input

An internal 110µA current source

charges an external capacitor to set the

soft-start rate. During a current limit

restart sequence, the internal current

source is reduced to 1.2µA to increase

the delay before retry.

DLY

Timing programming pin for

An external resistor to ground sets the

the LO and HO to SR1 and

timing for the non-overlap time of HO to

SR2 outputs.

SR1 and LO to SR2.

RES

Restart Timer

If cycle-by-cycle current limit is

exceeded during any cycle, a 22 µA

current is sourced to the RES pin

capacitor.If the RES capacitor voltage

reaches 2.5V, the soft-start capacitor will

be fully discharged and then released

with a pull-up current of 1.2µA. After the

first output pulse at LO (when SS

>COMP offset, typically 1V), the SS pin

charging current will revert to 110µA.

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