4 Meg x 4 EDO DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D47.pm5 – Rev. 3/97

©1997, Micron Technology, Inc.

2

4 MEG x 4

EDO DRAM

TECHNOLOGY, INC.

GENERAL DESCRIPTION (continued)

(the latter 11 bits for 2K and the latter 10 bits for 4K, address

pins A10 and A11 are “don’t care”). READ and WRITE

cycles are selected with the WE# input.

A logic HIGH on WE# dictates READ mode, while a logic

LOW on WE# dictates WRITE mode. During a WRITE

cycle, data-in (D) is latched by the falling edge of WE# or

CAS#, whichever occurs last. An EARLY WRITE occurs

when WE# is taken LOW prior to CAS# falling. A LATE

WRITE or READ-MODIFY-WRITE occurs when WE# falls

after CAS# is taken LOW. During EARLY WRITE cycles,

the data outputs (Q) will remain High-Z regardless of the

state of OE#. During LATE WRITE or READ-MODIFY-

WRITE cycles, OE# must be taken HIGH to disable the data

outputs prior to applying input data. If a LATE WRITE or

READ-MODIFY-WRITE is attempted while keeping OE#

LOW, no write will occur, and the data outputs will drive

read data from the accessed location.

The four data inputs and the four data outputs are routed

through four pins using common I/O, and pin direction is

controlled by WE# and OE#.

PAGE ACCESS

PAGE operations allow faster data operations (READ,

WRITE or READ-MODIFY-WRITE) within a row address-

defined page boundary. The PAGE cycle is always initiated

Figure 1

OE# CONTROL OF DQs

with a row address strobed-in by RAS#, followed by a

column address strobed-in by CAS#. CAS# may be

toggled-in by holding RAS# LOW and strobing-in different

column addresses, thus executing faster memory cycles.

Returning RAS# HIGH terminates the PAGE MODE of

operation, i.e., closes the page.

EDO PAGE MODE

The 4 Meg x 4 EDO DRAM provides EDO PAGE MODE,

which is an accelerated FAST PAGE MODE cycle. The

primary advantage of EDO is the availability of data-out

even after CAS# returns HIGH. EDO allows CAS# precharge

This elimination of CAS# output control allows pipeline

READs.

FAST PAGE MODE DRAMs have traditionally turned

the output buffers off (High-Z) with the rising edge of

CAS#. EDO PAGE MODE DRAMs operate like FAST

PAGE MODE DRAMs, except data will remain valid or

become valid after CAS# goes HIGH during READs, pro-

vided RAS# and OE# are held LOW. If OE# is pulsed while

RAS# and CAS# are LOW, data will toggle from valid data

to High-Z and back to the same valid data. If OE# is toggled

or pulsed after CAS# goes HIGH while RAS# remains

LOW, data will transition to and remain High-Z (refer to

,,

,,,

V

V

IH

IL

CAS#

V

V

IH

IL

RAS#

V

V

IH

IL

ADDR

,,

ROW

,,

,

COLUMN (A)

,,

,,,

,,

COLUMN (B)

,

,,,,

,,

DON’T CARE

UNDEFINED

,

,

,,

,,

V

V

IH

IL

OE#

V

V

IOH

IOL

OPEN

DQ

tOD

VALID DATA (B)

VALID DATA (A)

,

COLUMN (C)

,,,

,,,

VALID DATA (A)

tOE

,,

VALID DATA (C)

,

COLUMN (D)

,,,

,,

,

VALID DATA (D)

tOD

tOEHC

tOD

tOEP

tOES

The DQs go back to

The DQs remain High-Z

until the next CAS# cycle

The DQs remain High-Z

until the next CAS# cycle