AR0330_DS Rev. U Pub. 4/15 EN

76

©Semiconductor Components Industries, LLC,2015.

AR0330: 1/3-Inch CMOS Digital Image Sensor

Revision History

• Updated “Features” on page 1

• Updated Table 1, “Available Part Numbers,” on page 1

• Updated Table 1, “Key Parameters,” on page 1

• Removed Figure 2: Gain Stages

• Updated first paragraph of “General Description” on page 6

• Moved Working Modes section to follow Functional Overview

• Updated Figure 2: “Typical Configuration: Serial Four-Lane HiSPi Interface,” on

page 8

• Updated Figure 3: “Typical Configuration: Serial MIPI,” on page 9

• Updated Figure 4: “Typical Configuration: Parallel Pixel Data Interface,” on page 10

• Updated Table 5, Pin Descriptions; moved it under new section “Pin Descriptions” on

page 12

• Added Table 6, “CSP (HiSPi/MIPI) Package Pinout,” on page 13

• Added Figure 5: “CLCC Package Pin Descriptions,” on page 14

• Added “Electrical Characteristics” on page 18

• Added “Sensor Initialization” on page 15

• Added “Sequencer” on page 32

• Added “Sensor PLL” on page 32

• Added “Pixel Output Interfaces” on page 36

• Added “Sensor Readout” on page 46

• Updated “Subsampling” on page 49

• Added “Sensor Frame Rate” on page 51

• Added “Sensor Frame Rate” on page 51

• Updated “Slave Mode” on page 53

•Added “Frame Readout” on page 56

• Added “Two-Wire Serial Register Interface” on page 60

• Added “Packages” on page 69

Rev. C, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/3/10

• Updated Table 5, “Pin Descriptions,” on page 12.

• Added Figure 2: “Typical Configuration: Serial Four-Lane HiSPi Interface,” on page 8.

• Updated Figure 1: “Block Diagram,” on page 6.

• Updated pins and notes for Figure 2: “Typical Configuration: Serial Four-Lane HiSPi

Interface,” on page 8, Figure 3: “Typical Configuration: Serial MIPI,” on page 9 and

Figure 4: “Typical Configuration: Parallel Pixel Data Interface,” on page 10.

• Changed input clock range to 6-64 MHz

• Removed high dynamic range from general description

• Removed STANDBY pad from Figure 2: “Typical Configuration: Serial Four-Lane

HiSPi Interface,” on page 8 and Figure 4: “Typical Configuration: Parallel Pixel Data

Interface,” on page 10

• Changed HiSPi to SLVS in Table 5, “Pin Descriptions,” on page 12

• Updated slave mode section

• Updated Figure 36: “Slave Mode Active State and Vertical Blanking,” on page 53

• Updated Table 1, “Available Part Numbers,” on page 1

Rev. B, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/08/10

• Updated key parameters and general description

•Updated Table 3

• Removed two-wire serial interface