ML6694

9

FUNCTIONAL DESCRIPTION

TRANSMIT SECTION

100BASE-TX Operation

The transmitter accepts scrambled 5-bit symbols clocked

in at 25MHz and outputs MLT-3 signals onto the twisted-

pair media at 100Mbps. The on-chip transmit PLL converts

a 25MHz TTL-level clock at TXC to an internal 125MHz

bit clock. TXC from the ML6694 clocks scrambled

transmit symbols from the MAC into the ML6694's

TSM<4:0> input pins. Symbols from the TSM<4:0> inputs

are converted from parallel to serial form at the 125MHz

clock rate. The serial transmit data is converted to MLT-3

3-level code and driven differentialy out of the TPOUTP

and TPOUTN pins at nominal

± 2V levels with the proper

loads. The transmitter is designed to drive a center-tapped

transformer with a 2:1 winding ratio, so a differential 400

ohm load is used on the transformer primary to properly

terminate the 100 ohm cable and termination on the

secondary. The transformer’s center tap must be tied to

current in 100BASE-TX mode. Using a 1:1 transformer

would have required twice the output current and

increased the on-chip power dissipation. An external

2.49k

Ω, 1% resistor at the RTSET pin creates the correct

output levels at TPOUP/N.

10BASE-T

In 10BASE-T mode, the transmitter acts as a linear buffer

with a gain of 10. 10BASE-T inputs (Manchester data and

normal link pulses) at 10BTTXINP/N appear as full-swing

signals at TPOUTP/N in this mode. Inputs to the

10BTTXINP/N pins should have a nominal

±0.25V

differential amplitude and a common-mode voltage of

the 10BASE-T harmonic content requirements. The ML6694

does not provide any 10BASE-T transmit filtering.

RECEIVE SECTION

The receiver converts 3-level MLT-3 signals from the

twisted-pair media to 5-bit scrambled symbols at

RSM<4:0> with extracted clock at RXC. The adaptive

equalizer compensates for the distortion of up to 140m of

cable and attenuates cable-induced jitter, corrects for DC

baseline wander, and converts the MLT-3 signal to 2-level

NRZ. The receive PLL extracts clock from the equalized

signal, providing additional jitter attenuation, and clocks

the signal through the serial to parallel converter. The

resulting 5-bit symbols appear at RSM<4:0>. The

extracted clock appears at RXC. Resistor RGMSET sets

internal time constants controlling the adaptive equalizer’s

transfer function. RGMSET must be set to 9.53k

Ω (1%).

LOOPBACK

Tying

LPBK pin low places the part in loopback mode.

Data at TXD<4:0> are serialized, MLT-3 encoded,

equalized, then sent to receive PLL for clock recovery and

sent to the RXD<4:0> outputs.

In this mode, data at TXD<4:0> has to be valid 5-bit

symbol data.

ML6694 SCHEMATIC

Figure 2 shows a general design where the 5-bit and other

control signals interface to the controller. TXC is

connected to a 25MHz, 100ppm clock oscillator.

The inductors L1 and L2 are for the purpose of improving

return loss.

Capacitor C7 is recommended. It decouples some noise at

the inputs of the ML6694 and improves the Bit Error Rate

(BER) performance of the board. It is recommended

having a 0.1

and DGND planes are large enough for low inductance. If

splitting the two grounds and keeping the ground planes

large enough is not possible due to board space, you

could join them into one larger ground plane.

DIFFERENCES BETWEEN THE ML6694 AND ML6698

Both parts are pin to pin compatible and perform the same

functions. The only differences are:

1. SDO: The ML6694 has SDO (Signal Detect Output)

active in 100BASE-TX mode only, while the ML6698

has it active in both 10BASE-T and 100BASE-TX

modes.

2. SEL10/

100 or SEL100/10: The ML6694 has the

100BASE-TX mode active low and the 10BASE-T

mode active high (SEL10/

100). The ML6698 has the

opposite polarity where the 100BASE-TX mode is

active high and the 10BASE-T mode is active low

(SEL100/

10).