ML6694

7

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

MII (Media-Independent Interface)

TX Output Clock Frequency

25MHz frequency

–100

+100

ppm

Tolerance

TXC pulse width HIGH

14

ns

TXC pulse width LOW

14

ns

RXC pulse width HIGH

14

ns

RXC pulse width LOW

14

ns

Setup time, TSM<4:0> Data Valid

12

ns

to TXC Rising Edge (1.4V point)

Hold Time, TSM<4:0> Data

3

ns

Valid After TXC Rising Edge

(1.4V point)

Time that RSM<4:0> Data are

10

ns

Valid Before RXC Rising Edge

(1.4V point)

Time that RSM<4:0> Data are

10

ns

Valid After RXC Rising Edge

(1.4V point)

RXC 10% – 90% Rise Time

6ns

RXC 90%-10% Fall Time

6ns

Note 1.

Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.

Note 2.

Measured using the test circuit shown in Fig. 1, under the following conditions:

All resistors are 1% tolerance.

Note 3.

1.25V/RTSET.

Note 4.

Measured relative to ideal negative and positive signal 50% points, using the four successive MLT-3 transitions for the 01010101 bit sequence.

Note 5.

Time difference between 10% and 90% levels of the transition from the baseline voltage (nominally zero) to either the positive or negative peak signal voltage. The

times specified here correlate to the transition times defined in the ANSI X3T9.5 TP-PMD Rev 2.0 working draft, section 9.1.6, which include the effects of the

external network coupling transformer and EMI/RFI emissions filter.

Note 6.

Differential test load is shown in fig. 1 (see note 3).

Note 7.

Defined as the percentage excursion of the differential signal transition beyond its final adjusted value during the symbol interval following the transition. The

adjusted value is obtained by doing a straight line best-fit to an output waveform containing 14 bit-times of no transition preceded by a transition from zero to

either a positive or negative signal peak; the adjusted value is the point at which the straight line fit meets the rising or falling signal edge.

Note 8.

Symbol /J/ at TSM <4:0> sampled by TXC to first bit of /J/ at MDI.

Note 9.

First bit of /J/ at MDI to first rising edge of RXC after the last part of the /J/ appears at RSM <4:0>.

49.9

Ω

200

Ω

200

Ω

2:1

49.9

Ω

TPOUTP

TPOUTN

1

2

Figure 1. Test Circuit