5

ML6401

FUNCTIONAL DESCRIPTION

INTRODUCTION

The Micro Linear ML6401 is a single-chip video A/D

converter IC which is intended for analog to digital

conversion of 2Vp-p signals at rates up to 20MSPS.

Incorporating both bias and clock generation, it forms a

complete solution for data conversion. The operating

power dissipation is typically less than 200mW. The IC is

designed to offer low power dissipation and a high level

of integration resulting in an optimized solution. The IC

consists of an input track and hold, a three stage pipelined

A/D converter, digital error correction circuitry, internal

dual non-overlapping clock generator, and internal

voltage reference.

INPUT TRACK AND HOLD

The input track and hold consists of a differential

capacitor feedback amplifier. The input capacitance,

including pin protection and transmission gate, is 4pF.

The input to the track and hold can be driven differentially,

or single-ended. Single-ended operation uses an internal

or external reference to bias the negative input. The full

scale range can be set externally, or supplied from an

internal source. The track and hold samples the input

signal during the positive half cycle of the input clock,

cycle of the input clock. The settling time of the amplifier

is less than 20ns.

8

7

6

123456789

10

FREQUENCY

Typical Effective Bits versus Input Signal Frequency.

A/D CONVERTER

The A/D conversion is performed via a three stage

pipelined architecture. The first two stages quantize their

input signal to three bits, then subtract the result from the

input and amplify the difference by a factor of four. This

creates a residue signal which spans the full scale range of

the following converter. The subtraction and amplification

is performed via a differential capacitor feedback

amplifier, similar to the input track and hold. The third

stage quantizes the signal to four bits. One bit from each

of the last two stages is used for error correction.

The first stage A/D performs the conversion at the end of

the track and hold period, approximately one-half cycle

after the input was sampled. The second stage A/D

performs the conversion one half cycle later, after the

subtraction/amplification of the first stage has settled. The

third stage A/D performs the conversion after another one-

half cycle delay, when the second stage has settled. Error

correction is then performed, and, one clock cycle later,

data is transferred to the output latch. This permits the

data to be read 3 clocks after the sample was taken.

This technique results in lower input capacitance, lower

harmonic distortion, and higher signal to noise ratios than

the classical two step parallel technique, providing a

greater number of effective bits.

CLOCK GENERATION

The ML6401 typically requires an input clock that if

running at 20MHz would have a low time of 25ns, and a

high time of 25ns. This input is applied to a clock

generation circuit which creates the two non-overlapping

clock signals required by the feedback amplifiers.

Pipeline delay is the number of clock cycles between

conversion initiation and the associated output data being

made available. New output data is provided every clock

cycle.