4

ML6401

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Switching Characteristics

Maximum CLK Input Frequency

20

25

MHz

Clock Duty Cycle

CLK = 13.5MHz

40

60

%

CLK

≤ 20MHz

25

ns

CLK

≤ 20MHz

25

ns

Analog To Digital Converter Inputs — CLK

Low Level Input Voltage

0

0.8

V

High Level Input Voltage

2.4

V

Low Level Input Current

–5

+5

µA

High Level Input Current

–5

+5

µA

Input Capacitance

4.0

pF

Sampling Delay

5ns

Output Hold Time

412

10

ns

Output Delay Time

518

30

ns

Three-State Delay Time — Output Enable

10

25

ns

Three-State Delay Time — Output Disable

10

20

ns

Analog To Digital Converter Outputs — Digital

Low Level Output Voltage

0

0.6

V

High Level Output Voltage

2.4

V

Output Current in Three-State Mode

–20

+20

µA

Supplies

Analog, Digital & Output Supply Voltage

4.5

5.5

V

Analog Supply Current

Static

26

34

mA

Digital Supply Current

10

15

mA

Output Supply Current

4

10

mA

CLK

D0 TO D7

SAMPLE

OUT

N

N+1

N+2

N+3

N+4

N–3

N–2

N–1

N

N+1

TIMING DIAGRAM

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.