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LM5085MMX/NOPB датащи(PDF) 21 Page - Texas Instruments |
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LM5085MMX/NOPB датащи(HTML) 21 Page - Texas Instruments |
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21 / 33 page ![]() FB LM5085 PGATE GND Q1 L1 COUT RFB2 RFB1 VOUT GND D1 R4 R4 = VRIP(min) IOR(min) FB LM5085 PGATE GND Q1 L1 Cff COUT RFB2 RFB1 VOUT GND D1 R4 Cff = 3 x tON(max) (RFB1//RFB2) LM5085, LM5085-Q1 www.ti.com SNVS565I – NOVEMBER 2008 – REVISED AUGUST 2015 Typical Application (continued) (34) where tON(max) is the maximum on-time, which occurs at minimum VIN. The next larger standard value capacitor should be used for Cff. Figure 27. Reduced Ripple Configuration b) Lowest cost configuration: This configuration, shown in Figure 28, is the same as Figure 27 except Cff is removed. Since the ripple voltage at VOUT is attenuated by RFB2 and RFB1, the minimum ripple required at VOUT is equal to: VRIP(min) = 25mV x (RFB2 + RFB1)/RFB1 (35) The minimum value for R4 is calculated from: (36) where IOR(min) is the minimum ripple current, which occurs at minimum input voltage. Figure 28. Lowest Cost Ripple Generating Configuration Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: LM5085 LM5085-Q1 |
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