LM5085MMXSLASHNOPB datasheet(13/33 Pages) TI

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VIN x tON

tOFF

VFD + VESR t

'I =

(VOUT + VFD + VESR) x tOFF

'I =

(VIN - VOUT) x tON

tOFF(CL) =

(VFB x 0.93) + 0.28V

4.1 x 10

-6

x ((VIN/31) + 0.15)

LM5085, LM5085-Q1

www.ti.com

SNVS565I – NOVEMBER 2008 – REVISED AUGUST 2015

Feature Description (continued)

The CADJ capacitor filters noise from the ADJ pin, and helps prevent unintended switching of the current limit

comparator due to input voltage transients. The recommended value for CADJ is 1000pF.

7.3.5 Current Limit Off-Time

When the current through Q1 exceeds the current limit threshold, the LM5085 forces an off-time longer than the

normal off-time defined by Equation 1. See the graph “Off-Time vs. VIN and VFB”, or calculate the current limit off-

time from the following equation:

(10)

where VIN is the input voltage, and VFB is the voltage at the FB pin at the time current limit was detected. This

feature is necessary to allow the inductor current to decrease sufficiently to offset the current increase which

occurred during the on-time. During the on-time, the inductor current increases an amount equal to:

(11)

During the off-time the inductor current decreases due to the reverse voltage applied across the inductor by the

output voltage, the freewheeling diode’s forward voltage (VFD), and the voltage drop due to the inductor’s series

resistance (VESR). The current decrease is equal to:

(12)

The on-time in Equation 11 is shorter than the normal on-time since the PFET is shut off when the current limit

threshold is crossed. If the off-time is not long enough, such that the current decrease (Equation 12) is less than

the current increase (Equation 11), the current levels are higher at the start of the next on-time. This results in a

further decrease in on-time, since the current limit threshold is crossed sooner. A balance is reached when the

current changes in Equation 11 and Equation 12 are equal. The worst case situation is that of a direct short

circuit at the output terminals, where VOUT = 0V, as that results in the largest current increase during the on-time,

and the smallest decrease during the off-time. The sum of the diode’s forward voltage and the inductor’s ESR

voltage must be sufficient to ensure current runaway does not occur. Using Equation 11 and Equation 12, this

requirement can be stated as:

(13)

For tON in Equation 13, use the minimum on-time at the SW node. To determine this time period add the

“Minimum On-Time in Current Limit” specified in the Electrical Characteristics (tON-4) to the difference of the turn-

off and turn-on delays of the PFET. For tOFF use the value in the graph “Off-Time vs. VIN and VFB”, or use

Equation 10, where VFB is equal to zero volts. When using the minimum or maximum limits of those

specifications to determine worst case situations, the tolerance of the minimum on-time (tON-4) and the current

limit off-times (tOFF(CL1) through tOFF(CL4)) track each other over the process and temperature variations. A device

which has an on-time at the high end of the range will have an off-time that is at the high end of its range.

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