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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16LC712-04/SS датащи(PDF) 16 Page - Microchip Technology |
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PIC16LC712-04/SS датащи(HTML) 16 Page - Microchip Technology |
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16 / 108 page  PIC16C712/716 DS41106A-page 16 Preliminary © 1999 Microchip Technology Inc. 2.2.2.4 PIE1 REGISTER This register contains the individual enable bits for the peripheral interrupts. FIGURE 2-7: PIE1 REGISTER (ADDRESS 8Ch) Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIE — — — CCP1IE TMR2IE TMR1IE R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit7 bit0 bit 7: Unimplemented: Read as ‘0’ bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5-3: Unimplemented: Read as ‘0’ bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt |
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