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PIC876 датащи(PDF) 114 Page - Microchip Technology

номер детали PIC876
подробное описание детали  28/40-pin 8-Bit CMOS FLASH Microcontrollers
PDF  218 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC876 датащи(HTML) 114 Page - Microchip Technology

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PIC16F87X
DS30292C-page 112
 2001 Microchip Technology Inc.
REGISTER 11-2:
ADCON1 REGISTER (ADDRESS 9Fh)
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result reg-
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block dia-
gram of the A/D module is shown in Figure 11-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 11.1. After this
acquisition time has elapsed, the A/D conversion can
be started.
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1
= Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.
0
= Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
bit 6-4
Unimplemented: Read as '0'
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
Note 1: These channels are not available on PIC16F873/876 devices.
2: This column indicates the number of analog channels available as A/D inputs and
the number of analog channels used as voltage reference inputs.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
A = Analog input
D = Digital I/O
PCFG3:
PCFG0
AN7(1)
RE2
AN6(1)
RE1
AN5(1)
RE0
AN4
RA5
AN3
RA3
AN2
RA2
AN1
RA1
AN0
RA0
VREF+VREF-
CHAN/
Refs(2)
0000
AA
AA
A
A
A
A
VDD
VSS
8/0
0001
AA
AA
VREF+A
A
A
RA3
VSS
7/1
0010
DDD
A
A
A
A
A
VDD
VSS
5/0
0011
DDD
A
VREF+A
A
A
RA3
VSS
4/1
0100
DDD
D
A
D
A
A
VDD
VSS
3/0
0101
DDD
D
VREF+D
A
A
RA3
VSS
2/1
011x
DDD
D
D
D
D
D
VDD
VSS
0/0
1000
AA
AA
VREF+VREF-A
A
RA3
RA2
6/2
1001
DD
A
A
A
A
A
A
VDD
VSS
6/0
1010
DD
A
A
VREF+A
A
A
RA3
VSS
5/1
1011
DD
A
A
VREF+VREF-A
A
RA3
RA2
4/2
1100
DDD
A
VREF+VREF-A
A
RA3
RA2
3/2
1101
DDD
D
VREF+VREF-A
A
RA3
RA2
2/2
1110
DDD
D
D
D
D
A
VDD
VSS
1/0
1111
DDD
D
VREF+VREF-D
A
RA3
RA2
1/2



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