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PIC876 датащи(PDF) 111 Page - Microchip Technology |
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PIC876 датащи(HTML) 111 Page - Microchip Technology |
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111 / 218 page ![]() 2001 Microchip Technology Inc. DS30292C-page 109 PIC16F87X 10.4.2 USART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. Bit SREN is a “don't care” in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h). When setting up a Synchronous Slave Reception, fol- low these steps: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. 2. If interrupts are desired, set enable bit RCIE. 3. If 9-bit reception is desired, set bit RX9. 4. To enable reception, set enable bit CREN. 5. Flag bit RCIF will be set when reception is com- plete and an interrupt will be generated, if enable bit RCIE was set. 6. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register. 8. If any error occurred, clear the error by clearing bit CREN. 9. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS 0Bh, 8Bh, 10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices, always maintain these bits clear. |
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