LP3961, LP3964

www.ti.com

SNVS056J – MAY 2000 – REVISED JUNE 2015

Functional Block Diagram (continued)

Figure 19. LP3964 Adjustable Version Block Diagram

7.3 Feature Description

7.3.1 Short-Circuit Protection

The LP3961 and LP3964 are short-circuit protected and in the event of a peak overcurrent condition, the short-

circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts

down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the

thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the section

on thermal information for power dissipation calculations.

7.3.2 ERROR Flag Operation

The LP3961 produces a logic low signal at the ERROR flag pin when the output drops out of regulation due to

low input voltage, current limiting, or thermal limiting. This flag has a built-in hysteresis. The timing diagram in

Figure 20 shows the relationship between the ERROR pin and the output voltage. In this example, the input

voltage is changed to demonstrate the functionality of the ERROR flag.

The internal ERROR flag comparator has an open drain output stage. Hence, the ERROR pin should be pulled

high through a pull-up resistor. Although the ERROR pin can sink current of 1 mA, this current is an energy drain

from the input supply. Hence, the value of the pull-up resistor should be in the range of 100 k

Ω to 1 MΩ. The

ERROR pin must be connected to ground if this function is not used. It should also be noted that when the SD

pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown mode.

Copyright © 2000–2015, Texas Instruments Incorporated

Submit Documentation Feedback

11

Product Folder Links: LP3961 LP3964