PIC16C72-04SLASHSS datasheet(73/288 Pages) MICROCHIP

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DS30390E-page 73

PIC16C7X

10.1.4

CCP PRESCALER

There are four prescaler settings, speciﬁed by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off, or the CCP module is not in capture mode,

the prescaler counter is cleared. This means that any

reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore the ﬁrst capture may be from

a non-zero prescaler. Example 10-1 shows the recom-

mended method for switching between capture pres-

calers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

EXAMPLE 10-1: CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF

CCP1CON

;Turn CCP module off

MOVLW

NEW_CAPT_PS

;Load the W reg with

; the new prescaler

; mode value and CCP ON

MOVWF

CCP1CON

;Load CCP1CON with this

; value

10.2

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC2/CCP1 pin is:

• Driven High

• Driven Low

• Remains Unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt ﬂag bit CCP1IF is set.

FIGURE 10-3: COMPARE MODE

OPERATION BLOCK

DIAGRAM

Applicable Devices

72 73 73A 74 74A 76 77

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set ﬂag bit CCP1IF

(PIR1<2>)

match

RC2/CCP1

TRISC<2>

CCP1CON<3:0>

Mode Select

Output Enable

Special event trigger will:

reset Timer1, but not set interrupt ﬂag bit TMR1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>)

which starts an A/D conversion (CCP1 only for PIC16C72,

CCP2 only for PIC16C73/73A/74/74A/76/77).

10.2.1

CCP PIN CONFIGURATION

The user must conﬁgure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

10.2.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

10.2.3

SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen the CCP1

pin is not affected. Only a CCP interrupt is generated (if

enabled).

10.2.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

The special trigger output of CCP2 resets the TMR1

module is enabled).

For the PIC16C72 only, the special event trigger output

of CCP1 resets the TMR1 register pair, and starts an

A/D conversion (if the A/D module is enabled).

Note:

Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the

default low level. This is not the data latch.

Note:

The

special

event

trigger

from

the

CCP1and CCP2 modules will not set inter-

rupt ﬂag bit TMR1IF (PIR1<0>).

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