PIC18F010 datasheet(18/176 Pages) MICROCHIP

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PIC18F010/020

DS41142A-page 16

Preliminary

 2001 Microchip Technology Inc.

3.1

Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected. To take advantage of the POR cir-

cuitry, tie the MCLR pin directly (or through a resistor)

to VDD, or disable MCLR. This will eliminate external

oscillator components usually needed to create a

Power-on Reset delay. A maximum rise time for VDD is

specified (parameter D004). For a slow rise time, see

Figure 3-2.

When the device starts normal operation (exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature,...) must be met to ensure

operation. If these conditions are not met, the device

must be held in RESET until the operating conditions

are met. Brown-out Reset may be used to meet the

voltage start-up condition.

FIGURE 3-2:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

3.2

Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out

(parameter #33) only on power-up from the POR or

BOR, if enabled. The Power-up Timer operates on an

internal oscillator. The chip is kept in RESET as long as

the PWRT is active. The PWRT’s time delay allows

VDD to rise to an acceptable level. A configuration bit is

provided to enable/disable the PWRT.

The power-up time delay will vary from chip-to-chip due

to VDD, temperature and process variation. See DC

parameter #33 for details.

3.3

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over (parameter #32). This ensures that

the crystal oscillator or resonator has started and

stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

3.4

Brown-out Reset (BOR)

A configuration bit, BOREN, can disable (if clear/

programmed), or enable (if set) the Brown-out Reset

circuitry. If VDD falls below parameter D005 for greater

than parameter #35, the brown-out situation will reset

the chip. A RESET may not occur if VDD falls below

parameter D005 for less than parameter #35. The chip

will remain in Brown-out Reset until VDD rises above

BVDD. The Power-up Timer will then be invoked and

will keep the chip in RESET an additional time delay

(parameter #33). If VDD drops below BVDD while the

Power-up Timer is running, the chip will go back into a

Brown-out Reset and the Power-up Timer will be initial-

ized. Once VDD rises above BVDD, the Power-up Timer

will execute the additional time delay.

Note 1: External Power-on Reset circuit is required only

if the VDD power-up slope is too slow. The diode

D helps discharge the capacitor quickly when

VDD powers down.

2: R < 40k

Ω is recommended to make sure that

the voltage drop across R does not violate the

device’s electrical specification.

3: R1 = 100

Ω to 1kΩ will limit any current flowing

into MCLR from external capacitor C, in the

event of MCLR/VPP pin breakdown due to

Electrostatic Discharge (ESD), or Electrical

Overstress (EOS).

VDD

MCLR

PIC18F010/020

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