6

FN3976.4

September 17, 2015

DIRECTION Input Control terminal. The MOS output transistor

pair chosen for conduction is determined by the logic level

applied to the DIRECTION control; resulting in either clockwise

(CW) or counter-clockwise (CCW) shaft rotation.

When the BRAKE terminal is switched high (while holding

the ENABLE input high), the gates of both Q2 and Q4 are

driven high. Current flowing through Q2 (from the motor

terminal OUTA) at the moment of Dynamic Braking will

connection, and then continue through diode D4 to the motor

terminal OUTB. As such, the resistance of the motor winding

(and the series-connected path) dissipates the kinetic

energy stored in the system. Reversing rotation, current

flowing through Q4 (from the motor terminal OUTB), at the

moment of Dynamic Braking, would continue to flow through

diode D2 to the motor terminal OUTA, to dissipate the stored

kinetic energy as previously described.

terminals for the Control Logic, the lowest practical supply

voltage for proper logic control should be no less than 2.0V.

than the Absolute Maximum Supply Voltage rating.

Terminals A1, B1, A2, B2, ENA and ENB are internally

connected to protection circuits intended to guard the CMOS

gate-oxides against damage due to electrostatic discharge.

(See Figure 3) Inputs ENA, ENB, A1, B1 A2 and B2 have

CD74HCT4000 Logic Interface Protection and Level

Converters for TTL or CMOS Input Logic. These inputs are

designed to typically provide ESD protection up to 2kV.

However, these devices are sensitive to electrostatic

discharge. Proper I.C. handling procedures should be

followed.

INPUT

LEVEL

CONV.

FIGURE 3. LOGIC INPUT ESD INTERFACE PROTECTION

A1

A2

ENA

(DIR)

(BRAKE)

(ENABLE)

OT AND OC

PROTECT

N-DR

LIMIT

P-DR

LIMIT

Q2

D2

Q1

D1

OUTA

B1

B2

ENB

(DIR)

(BRAKE)

(ENABLE)

OT AND OC

PROTECT

N-DR

LIMIT

P-DR

LIMIT

Q4

D4

Q3

D3

OUTB

FIGURE 4. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS

HIP4020