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HIP2103 датащи(PDF) 19 Page - Intersil Corporation |
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HIP2103 датащи(HTML) 19 Page - Intersil Corporation |
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19 / 21 page ![]() HIP2103, HIP2104 19 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8276.0 November 27, 2013 For additional products, see www.intersil.com/en/products.html Submit Document Feedback • Large power components (Power FETs, Electrolytic caps, power resistors, etc.) have internal parasitic inductance which cannot be eliminated. This must be accounted for in the PCB layout and circuit design. • If you simulate your circuits, consider including parasitic components especially parasitic inductance. General EPAD Heatsinking Considerations The EPAD of the HIP2103, HIP2104 is electrically connected to VSS through the IC substrate. The epad has two main functions: to provide a quiet signal ground and to provide heat sinking for the IC. The EPAD must be connected to a ground plane and switching currents from the driven FETs should not pass through the ground plane under the IC. Figure 28 is a PCB layout example of how to use vias to remove heat from the IC through the EPAD. For maximum heatsinking, it is recommended that a ground plane, connected to the EPAD, be added to both sides of the PCB. A via array, within the area of the EPAD, will conduct heat from the EPAD to the GND plane on the bottom layer. The number of vias and the size of the GND planes required for adequate heatsinking is determined by the power dissipated by the HIP2103, HIP2104, the air flow, and the maximum temperature of the air around the IC. Note that a separate plane is added under the high side drive circuits and is connected to HS. In a manner similar to the ground plane, the HS plane provides the lowest possible parasitic inductance for the HO/HS gate drive current loop. See AN1899 “HIP2103, HIP2104 3-phase, Full, or Half Bridge Motor Driver” for an example of PCB layout of a real application. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support VDD EPAD GND PLANE COMPONENT LAYER HI LI LS HB HO HS LO EPAD GND PLANE BOTTOM LAYER VDD HI LI LS HB HO HS LO This plane is connected to HS and is under all high side driver circuits FIGURE 28. TYPICAL PCB PATTERN FOR THERMAL VIAS Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE November 27, 2013 FN8276.0 Initial Release |
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