HIP2103, HIP2104

18

FN8276.0

November 27, 2013

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But this solution also has its limitations. Depending on the value

may dissipate significant power because the voltage on the

capacitor is switching between the bridge voltage and ground.

switching frequency for most motor drives is <20kHz and the

transferred to the gate of the high-side FET when the low-side FET

turns on. When the phase node goes low, a voltage is impressed

cap is very large, the voltage on the gate will approach the bridge

voltage turning on the high-side FET resulting with shoot-through.

determined by the turn-on time of the low side FET. As the

low-side FET is turning on, the charge on the filter cap is

relatively large gate capacitance of the high-side FET is in parallel

than 1V.

The emphasis of suppressing transients on the HS pin has been

with negative transients. Please note that a similar transients

with a positive polarity occurs when the low-side FET turns off.

This is usually not a problem unless the bridge voltage is close to

the maximum rated operating voltage of 50V. Note that the

maximum voltage ratings for the HS and HB nodes also must be

observed when the positive transient occurs.

The maximum rating for (VHB - VHS) must also not be

overlooked. When a negative transient, Vneg, is present on the

HS pin, the voltage differential across HB and HS will approach

VDD + Vneg. If the transient duration is short compared to the

charging time constant of the boot diode and boot capacitor, the

voltage across HB and HS is not significantly affected. However,

another source of negative voltage on the HS pin will more likely

increase the boot capacitor voltage. While current is flowing from

the source to drain of the low-side FET during the dead time, the

current flows through body diode of the FET. Depending on the

size of the FET and the amplitude of the reverse current, the

voltage across the diode can be as high as -1.5V and much

higher during a load fault. Because this negative voltage has little

impedance, the boot capacitor can charge to a voltage greater

than VDD (for example VDD + 1.5V). It may be necessary to either

clamp the voltage as described in Figures 25 through 27 and/or

keep the dead time as short as possible.

General PCB Layout Guidelines

The AC performance of the HIP2103, HIP2104 depends

significantly on the design of the PC board. The following layout

design guidelines are recommended to achieve optimum

performance:

• Place the driver as close as possible to the driven power FET.

• Understand where the switching power currents flow. The high

amplitude di/dt currents of the driven power FET will induce

significant voltage transients on the associated traces.

• Keep power loops as short as possible by paralleling the

source and return traces.

• Use planes where practical; they are usually more effective

than parallel traces.

• Avoid paralleling high amplitude di/dt traces with low level

signal lines. High di/dt will induce currents and consequently,

noise voltages in the low level signal lines.

• When practical, minimize impedances in low level signal

circuits. Noise, magnetically induced on a 10kΩ resistor, is 10x

larger than the noise on a 1kΩ resistor.

• Be aware of magnetic fields emanating from motors and

inductors. Gaps in the magnetic cores of these structures are

especially bad for emitting flux.

• If you must have traces close to magnetic devices, align the

traces so that they are parallel to the flux lines to minimize

coupling.

• The use of low inductance components such as chip resistors

and chip capacitors is highly recommended.

• Use decoupling capacitors to reduce the influence of parasitic

these caps must also have the shortest possible conduction

paths. If vias are used, connect several paralleled vias to

reduce the inductance of the vias.

• It may be necessary to add resistance to dampen resonating

parasitic circuits especially on LO and LO. If an external gate

resistor is unacceptable, then the layout must be improved to

minimize lead inductance.

• Keep high dv/dt nodes away from low level circuits. Guard

banding can be used to shunt away dv/dt injected currents

from sensitive circuits.

• Avoid having a signal ground plane under a high amplitude

dv/dt circuit. The parasitic capacitance of a ground plane, Cp,

relative to the high amplitude dv/dt circuit will result in

injected (Cp x dv/dt) currents into the signal ground paths

where C is the parasitic capacitance of the ground plane.

• Do power dissipation and voltage drop calculations of the

power traces. Many PCB/CAD programs have built in tools for

calculation of trace resistance. The internet is also a good

source for resistance calculators for PCB trace resistance.

FIGURE 27. RESISTOR AND CAPACITOR NEGATIVE TRANSIENT FILTER

VSS

HS

LO

HO

Inductive

Load

HB

+

_