FX929B datasheet(17/48 Pages) CMLMICRO

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4-Level FSK Modem Data Pump

FX929B

D/929B/1

SFP: Search for Frame Preamble

This task causes the modem to search the received signal for a valid Frame Preamble, consisting of a 24-

symbol Frame Sync sequence followed by Station ID data which has a correct CRC0 checksum.

The task continues until a valid Frame Preamble has been found.

The search consists of four stages:

First of all the modem will attempt to match the incoming symbols against the Frame Synchronisation

pattern to within the tolerance defined by the FSTOL bits of the Control Register.

Once a match has been found, the modem will read in the following 'S' symbol, place it in the SVAL

bits of the Status Register then set the SRDY bit to '1'. (The IRQ bit of the Status Register will also be

set to '1' at this time if the SSIEN bit of the Mode Register is '1').

The modem will then read the next 22 symbols as station ID data. They will be decoded and the CRC0

checked. If this is incorrect, the modem will resume the search, looking for a fresh Frame Sync

pattern.

If the received CRC0 is correct, the following 'S' symbol will be read into the SVAL bits of the Status

decoded Station ID bytes placed into the Data Block Buffer.

On detecting that the BFREE bit of the Status Register has gone to '1', the µC should read the 3 Station ID

bytes from the Data Block Buffer then write the next task to the modem's Command Register.

RHB: Read Header Block

This task causes the modem to read the next 69 symbols as a 'Header' Block. It will strip out the 'S' symbols

then de-interleave and decode the remaining 66 symbols, placing the resulting 10 data bytes and the 2

received CRC1 bytes into the Data Block Buffer, and setting the BFREE and IRQ bits of the Status Register to

'1' when the task is complete to indicate that the µC may read the data from the Data Block Buffer and write

the next task to the modem's Command Register.

The CRCERR bit of the Status Register will be set to '1' or '0' depending on the validity of the received CRC1

checksum bytes.

As each of the 3 'S' symbols of a block is received, the SVAL bits of the Status Register will be updated and

the SRDY bit set to '1'. (If the SSIEN bit of the Mode Register is '1', then the Status Register IRQ bit will also

be set to '1'.) Note that when the third 'S' symbol is received, the SRDY bit will be set to '1' coincidentally with

the BFREE bit also being set to '1'.

RILB: Read 'Intermediate' or 'Last' Block

This task causes the modem to read the next 69 symbols as an 'Intermediate' or 'Last' block (the µC can tell

from the 'Header' block how many blocks are in the frame, and hence when to expect the 'Last' block).

In each case, it will strip out the 3 'S' symbols, de-interleave and decode the remaining 66 symbols and place

the resulting 12 bytes into the Data Block Buffer, setting the BFREE and IRQ bits of the Status Register to '1'

when the task is complete.

If an 'Intermediate' block is received then the µC should read out all 12 bytes from the Data Block Buffer and

ignore the CRCERR bit of the Status Register, for a 'Last' block the µC need only read the first 8 bytes from

the Data Block Buffer, and the CRCERR bit in the Status Register will reflect the validity of the received CRC2

checksum.

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