dog-timeout period, WDO goes low 70ns after the

falling edge of WDPO and remains low until the next

transition at WDI (Figure 5). A flip-flop can force the

system into a hardware shutdown if there are two suc-

cessive watchdog faults (Figure 6). WDO has a 2 x TTL

output characteristic.

Watchdog-Pulse Output

As described in the preceding section, WDPO can be

used as the clock input to an external D flip-flop. Upon

the absence of a watchdog edge or pulse at WDI at the

end of a watchdog-timeout period, WDPO will pulse low

for 1ms. The falling edge of WDPO precedes WDO by

70ns. Since WDO is high when WDPO goes low, the

flip-flop’s Q output remains high as WDO goes low

(Figure 5). If the watchdog timer is not reset by a transi-

tion at WDI, WDO remains low and WDPO clocks a

logic low to the Q output, causing the MAX791 to latch

in reset. If the watchdog timer is reset by a transition at

WDI, WDO goes high and the flip-flop’s Q output

remains high. Thus, a system shutdown is only caused

by two successive watchdog faults.

The internal pull-up resistors associated with WDO and

these outputs directly to CMOS logic that is powered

mode), excessive current will flow from WDO or

WDPO through the protection diode(s) of the CMOS-

logic inputs to ground.

Selecting an Alternative Watchdog

Timeout Period

SWT input controls the watchdog-timeout period.

watchdog-timeout period. Select an alternative timeout

period by connecting a capacitor between SWT and

GND. Do not leave SWT floating, and do not connect it

to ground. The following formula determines the watch-

dog-timeout period:

Watchdog Timeout Period = 2.1 x (capacitor value

in nF) ms

This formula is valid for capacitance values between

4.7nF and 100nF (see the Watchdog Timeout vs.

Timing Capacitor graph in the

Typical Operating

Characteristics). SWT is internally connected to a

±100nA (typ) current source, which charges and dis-

charges the timing capacitor to create the oscillator fre-

quency that sets the watchdog timeout period (see

Connecting a Timing Capacitor to SWT in the

Applications Information section).

Microprocessor Supervisory Circuit

10

______________________________________________________________________________________

MAX791

CLOCK

CD4013

GND

MR

0.1

µF

4.7k

*SETS Q HIGH ON POWER-UP

VBATT

RESET

WDI

WDPO

WDO

µP POWER

µP

RESET

TWO

CONSECUTIVE

WATCHDOG

FAULT

INDICATIONS

I/O

Q

D

Q

SET

2

15

11

LOWLINE

NMI

INTERRUPT

10

16

1/6 74HC04

14

1

5

3

14

3

2

7

4

6

*1

µF

+5V

1

9

4

REACTIVATE

+5V

3.6V

Figure 6. Two consecutive watchdog faults latch the system in reset.